CN-122028427-A - Technological method applied to flash memory device manufacturing

Abstract

The application discloses a process method applied to manufacturing of a flash memory device, which comprises the steps of providing a substrate, forming a region for forming a pattern structure on the substrate, comprising an active region of a flash memory unit, sequentially forming a first oxide layer, a floating gate and a hard mask layer on the front surface of the substrate of the active region from bottom to top, forming a groove between the active regions, filling an isolation layer in the groove, wherein the top of the isolation layer is lower than the top of the hard mask layer and higher than the top of the floating gate, forming a second oxide layer on the back surface of the substrate, forming a blocking layer on the second oxide layer, forming a third oxide layer on the blocking layer, performing ion implantation to dope the floating gate, performing dry etching to enable the top of the isolation layer to be lower than the top of the floating gate and higher than the top of the first oxide layer, covering the exposed region of the floating gate after etching by a protective layer and thinning the hard mask layer, removing the blocking layer and the third oxide layer, and removing the hard mask layer.

Inventors

• ZHOU ZIREN
• ZHU JINGRUN
• LIU XIANZHOU
• YAO JIE
• WEI LAI

Assignees

• 华虹半导体制造(无锡)有限公司
• 上海华虹宏力半导体制造有限公司
• 华虹半导体(无锡)有限公司

Dates

Publication Date

20260512

Application Date

20260130

Claims (6)

1. 1. A process method applied to manufacturing a flash memory device, comprising: Providing a substrate, wherein a region for forming a pattern structure on the substrate comprises an active region of a flash memory cell, a first oxide layer, a floating gate and a hard mask layer are sequentially formed on the front surface of the substrate of the active region from bottom to top, a groove is formed between the active regions, an isolation layer is filled in the groove, the top of the isolation layer is lower than the top of the hard mask layer and higher than the top of the floating gate, a second oxide layer is formed on the back surface of the substrate, a barrier layer is formed on the second oxide layer, and a third oxide layer is formed on the barrier layer; Ion implantation is carried out, and the floating gate is doped; carrying out dry etching to enable the top of the isolation layer to be lower than the top of the floating gate and higher than the top of the first oxide layer, wherein after etching, the exposed area of the floating gate is covered by a protective layer formed in the etching process and the hard mask layer is thinned; removing the barrier layer and the third oxide layer; and removing the hard mask layer.
2. 2. The method of claim 1, wherein the isolation layer, the first oxide layer, the second oxide layer, and the third oxide layer comprise a silicon dioxide layer.
3. 3. The method of claim 2, wherein the hard mask layer and the barrier layer comprise a silicon nitride layer.
4. 4. A method according to claim 3, characterized in that the etching effect is achieved during dry etching by increasing the etching selectivity of silicon nitride and silicon dioxide and decreasing the etching rate.
5. 5. The method of claim 3, wherein the hard mask layer is removed by wet etching.
6. 6. The method of claim 5, wherein the agent used in removing the hard mask layer by wet etching comprises phosphoric acid.

Description

Technological method applied to flash memory device manufacturing Technical Field The application relates to the technical field of semiconductor devices and integrated circuits, in particular to a process method applied to manufacturing of flash memory devices. Background Memories using nonvolatile memory (NVM) technology are widely used in electronic products with memory functions, such as smart phones, tablet computers, digital cameras, universal serial bus flash memory discs (universal serial bus FLASH DISK, USB flash memory discs, abbreviated as "USB discs"). Among NVM memories, NOR flash (NOR) devices are widely used due to higher writing speed and higher storage capacity. Referring to fig. 1, a schematic cross-sectional view of ion implantation of a floating gate during fabrication of a NOR flash memory device provided in the related art is shown. Illustratively, as shown in fig. 1, a first oxide layer 121, a Floating Gate (FG) 131 and a Hard Mask (HM) layer 141 are sequentially formed in an active region (ACTIVE AREA, AA) of a flash memory cell (cell) region on a substrate 110 from bottom to top, a groove 301 is formed between the active regions, the groove 301 is filled with an isolation layer 111, the top of the isolation layer 111 is lower than the top of the hard mask layer 141 and higher than the top of the floating gate 131, a second oxide layer 122 is formed on the back surface of the substrate 110, a barrier layer 142 is formed on the second oxide layer 122, and a third oxide layer 123 is formed on the barrier layer 142. Ion implantation may be performed to dope the floating gate 131. Referring to fig. 2, a schematic cross-sectional view of an isolation layer after etching and thinning is shown. Illustratively, as shown in fig. 2, the spacer 111 may be thinned by a dry etching process while the top of the thinned spacer 111 is substantially flush with the top of the floating gate 131. Referring to fig. 3, a schematic cross-sectional view is shown after removal of the third oxide layer, the hard mask layer and the isolation layer. Illustratively, as shown in fig. 3, the third oxide layer 123, the hard mask layer 141, and the isolation layer 142 may be removed by a wet etching process. In improving the fabrication process of NOR flash memory to further reduce its size, increasing the coupling between the Control Gate (CG) and the floating gate is advantageous in maintaining the process window of the stored data "0", "1" of the flash memory cell. While the thinning etch process for spacer 111 defines a height difference between spacer 111 and floating gate 131 that is related to the coupling coefficient between the control gate and floating gate. In the manufacturing process of the NOR flash memory device provided in the related art, if the height difference between the isolation layer 111 and the floating gate 131 needs to be increased, the etching amount in the thinning etching process needs to be increased, so that more plasmas are introduced, the floating gate 131 is easy to damage, the floating gate 131 is exposed and is easy to be separated out due to the obvious lateral etching effect in the etching process, and meanwhile, the hard mask layer 141 is usually thicker, and can be thoroughly removed after being soaked for a longer time in the subsequent wet etching, so that the floating gate 131 is also damaged. Disclosure of Invention The application provides a process method applied to the manufacture of a flash memory device, which can solve the problem that the manufacturing method of the flash memory device provided in the related art is easy to cause floating gate damage after the height difference of an isolation layer and a floating gate is improved, and comprises the following steps: Providing a substrate, wherein a region for forming a pattern structure on the substrate comprises an active region of a flash memory cell, a first oxide layer, a floating gate and a hard mask layer are sequentially formed on the front surface of the substrate of the active region from bottom to top, a groove is formed between the active regions, an isolation layer is filled in the groove, the top of the isolation layer is lower than the top of the hard mask layer and higher than the top of the floating gate, a second oxide layer is formed on the back surface of the substrate, a barrier layer is formed on the second oxide layer, and a third oxide layer is formed on the barrier layer; Ion implantation is carried out, and the floating gate is doped; carrying out dry etching to enable the top of the isolation layer to be lower than the top of the floating gate and higher than the top of the first oxide layer, wherein after etching, the exposed area of the floating gate is covered by a protective layer formed in the etching process and the hard mask layer is thinned; removing the barrier layer and the third oxide layer; and removing the hard mask layer. In some embodiments, the isolation layer, the first ox