CN-122028428-A - Semiconductor device and method for manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a first area and a second area, and the second area is provided with a groove; the semiconductor device comprises a first shallow trench isolation structure, a second shallow trench isolation structure, a first gate oxide layer, a second gate oxide layer, a first shallow trench isolation structure, a second shallow trench isolation structure, a first gate oxide layer, a second gate oxide layer, a first gate oxide layer and a second gate oxide layer, wherein the first shallow trench isolation structure and the second shallow trench isolation structure are respectively positioned in a first area and a second area, and the first shallow trench isolation structure is higher than the second shallow trench isolation structure in the first direction. According to the semiconductor device and the manufacturing method thereof, the grooves are formed in the first area, and the height of the first shallow trench isolation structure is larger than that of the second shallow trench isolation structure, so that the large channel length is realized in the first area, the fin-like transistor structure is formed in the second area, and the short channel effect in the semiconductor device is relieved.

Inventors

• ZHANG QUAN
• YAO LAN
• ZHOU LU

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260512

Application Date

20210831

Claims (20)

1. 1. A three-dimensional memory device comprising an array of memory cells and peripheral circuitry, the peripheral circuitry comprising: a substrate including a first bump structure and a second bump structure; The first oxide layer is positioned on the first protruding structure and at least surrounds the first protruding structure on three sides, and the second oxide layer is positioned on the second protruding structure and surrounds the second protruding structure on at least three sides; And the first isolation structure is positioned between the first protruding structure and the second protruding structure, and the first oxide layer and the second oxide layer are at least partially positioned on the first isolation structure and are in contact with the first isolation structure.
2. 2. The three-dimensional memory device of claim 1, further comprising a first gate layer, the first gate layer is located above the first oxide layer and the second oxide layer and covers the first oxide layer and the second oxide layer.
3. 3. The three-dimensional storage device of claim 1, further comprising: a third oxide layer over the substrate, and And the second gate layer is positioned on the second oxide layer, and the thickness of the third oxide layer is larger than that of the first oxide layer and the second oxide layer.
4. 4. The three-dimensional storage device of claim 3, further comprising: and the second isolation structure is formed in the substrate and is positioned between the first oxide layer and the third oxide layer, and the height of the second isolation structure is larger than that of the first isolation structure.
5. 5. The three-dimensional storage device of claim 4, wherein bottoms of the first and second isolation structures are aligned.
6. 6. The three-dimensional memory device of claim 3, wherein the substrate comprises a first recess in which the third oxide layer is at least partially formed, the third oxide layer comprising a second recess located at a side of the third oxide layer at the first recess and remote from the substrate, the second gate layer being at least partially located in the second recess.
7. 7. The three-dimensional memory device of claim 6, wherein the second gate layer side remote from the substrate is a planar surface.
8. 8. The three-dimensional memory device of any one of claims 1-7, wherein the three-dimensional memory device is a NAND chip.
9. 9. A three-dimensional memory device comprising an array of memory cells and peripheral circuitry, the peripheral circuitry comprising: a substrate comprising a raised structure; A first oxide layer over the raised structure and surrounding the raised structure on at least three sides; a first isolation structure located at a side of the bump structure and contacting the bump structure, and And the first grid electrode layer is positioned on the first oxide layer and covers the first oxide layer, and the bottom of the first oxide layer is in contact with the isolation structure.
10. 10. The three-dimensional memory device of claim 9, wherein a bottom of the first gate layer is in contact with the first isolation structure.
11. 11. The three-dimensional storage device of claim 9, further comprising: a second oxide layer over the substrate, and And the second gate layer is positioned on the second oxide layer, and the thickness of the second oxide layer is larger than that of the first oxide layer.
12. 12. The three-dimensional storage device of claim 11, further comprising: and the second isolation structure is formed in the substrate and is positioned between the first oxide layer and the second oxide layer, and the height of the second isolation structure is larger than that of the first isolation structure.
13. 13. The three-dimensional storage device of claim 12, wherein bottoms of the first and second isolation structures are aligned.
14. 14. The three-dimensional memory device of claim 12, wherein the substrate comprises a first recess, the second oxide layer is at least partially formed in the first recess, and a bottom of the second isolation structure is lower than a bottom of the first recess.
15. 15. The three-dimensional memory device of claim 14, wherein the second oxide layer comprises a second recess at a side of the third oxide layer at the first recess and away from the substrate, the second gate layer being at least partially in the second recess.
16. 16. The three-dimensional memory device of claim 15, wherein the side of the second gate layer remote from the substrate is a planar surface.
17. 17. The three-dimensional memory device of claim 11, wherein upper surfaces of the first gate layer and the second gate layer are aligned.
18. 18. The three-dimensional memory device of any one of claims 9-17, wherein the three-dimensional memory device is a NAND chip.
19. 19. A three-dimensional memory device comprising an array of memory cells and peripheral circuitry, the peripheral circuitry comprising: a substrate comprising a raised structure; A first transistor including a first gate oxide layer and a first gate oxide layer, the first gate oxide layer being over the raised structure and surrounding the raised structure on at least three sides, the first gate layer being over the first gate oxide layer and surrounding the first gate oxide layer on at least three sides, and The second transistor comprises a second gate electrode layer and a second gate electrode oxide layer, and the thickness of the first gate electrode oxide layer is smaller than that of the second gate electrode oxide layer.
20. 20. The three-dimensional memory device of claim 19, further comprising a first isolation structure located on a side of and in contact with the raised structure, the first gate layer and the first gate oxide layer being at least partially located over and in contact with the first isolation structure.

Description

Semiconductor device and method for manufacturing the same The present application is a divisional application, the international application number of the original application is PCT/CN2021/115853, the national application number of the original application into the country is 202180003571.9, the original application date is 2021, 08 and 31, and the whole content of the original application is incorporated by reference. Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background With the increasing demands on the storage density of 3D-NAND flash memory, the feature sizes of existing devices are also shrinking. On a control chip of the 3D-NAND flash memory, a high-voltage device region and a low-voltage device region are generally formed at the same time, and as the feature size of the device is reduced to a certain node, a serious short channel effect occurs in field effect transistors in the existing high-voltage device region and low-voltage device region. In addition, because the high-voltage device region and the low-voltage device region have different requirements on breakdown voltage, it is difficult to manufacture a semiconductor device which can avoid serious short-channel effect and simultaneously meet the requirements on breakdown voltage of different device regions based on the prior art. Accordingly, the prior art has drawbacks and needs to be improved and developed. Disclosure of Invention The invention provides a semiconductor device and a manufacturing method thereof, which can effectively avoid serious short channel effect and simultaneously meet the breakdown voltage requirements of different device areas. In order to solve the problems, the invention provides a manufacturing method of a semiconductor device, which comprises the steps of providing a substrate, forming a groove on the first area, forming a first oxide layer on the first area and a second oxide layer on the second area to form a first gate oxide layer on the groove, forming a first mask layer on the first oxide layer and the second oxide layer, forming a first shallow trench isolation structure and a second shallow trench isolation structure on the first area and the second area respectively, wherein the height of the first shallow trench isolation structure in a first direction is larger than that of the second shallow trench isolation structure in the first direction, removing the first mask layer, and forming a second gate oxide layer on the second area and the second shallow trench isolation structure. The substrate further comprises a third region, and forming the groove on the first region comprises forming the groove and the scribing groove on the first region and the third region respectively. The first shallow trench isolation structure and the second shallow trench isolation structure are formed on the first area and the second area respectively, and the method comprises the steps of etching the first mask layer and the substrate to form isolation grooves in the substrate, filling spacers in the isolation grooves to form the first shallow trench isolation structure in the first area, and etching the spacers distributed in the second area to form the second shallow trench isolation structure. The forming of the second gate oxide layer on the second region and the second shallow trench isolation structure comprises etching the second oxide layer, and forming the second gate oxide layer on the surface of the substrate of the second region and the side wall of the isolation trench. The thickness of the first gate oxide layer is larger than that of the second gate oxide layer. The method comprises the steps of forming a first gate electrode layer on the surface of a first gate oxide layer after forming a second gate oxide layer located in a second area, and forming a second gate electrode layer on the surface of the second gate oxide layer. And forming the second gate oxide layer by adopting a thermal oxidation process. The first mask layer is made of silicon nitride. The first region is used for forming a concave grid type field effect transistor, and the second region is used for forming a fin type field effect transistor. The invention also provides a semiconductor device, which comprises a substrate, a first shallow trench isolation structure, a second shallow trench isolation structure, a first gate oxide layer, a second gate oxide layer, a first gate oxide layer and a second gate oxide layer, wherein the substrate comprises a first area and a second area, the second area is provided with a groove, the first shallow trench isolation structure and the second shallow trench isolation structure are respectively arranged in the first area and the second area, the height of the first shallow trench isolation structure in a first direction is larger than that of the second shallow trench isolation