CN-122028429-A - Memory device and method of manufacturing the same

Abstract

A memory device includes a laminate in which conductive layers and interlayer insulating layers are alternately laminated in a lamination direction, and a method of manufacturing the memory device. The memory device further includes a chip protector surrounding the chip region of the laminate, the chip protector penetrating the laminate in the lamination direction. The memory device also includes a test electrode electrically coupled to the chip protector. The test electrodes are spaced apart from each other and at least a portion of the chip area is disposed between the test electrodes.

Inventors

• JIN ZAIHAO

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260512

Application Date

20250512

Priority Date

20241107

Claims (20)

1. 1.A memory device, the memory device comprising: a laminate in which conductive layers and interlayer insulating layers are alternately laminated in a lamination direction; A chip protector surrounding a chip region of the laminate, the chip protector penetrating the laminate in the lamination direction, and A test electrode electrically coupled to the chip protector, Wherein the test electrodes are spaced apart from each other and at least a portion of the chip area is disposed between the test electrodes.
2. 2. The memory device of claim 1, wherein the chip protector comprises: A vertical structure penetrating the laminate; At least one upper line and at least one upper plug, the at least one upper line and the at least one upper plug being located above the laminate, and At least one lower line and at least one lower plug, the at least one lower line and the at least one lower plug being located below the laminate.
3. 3. The memory device of claim 2, wherein at least one of the test electrodes is coupled to the at least one upper line.
4. 4. The memory device of claim 2, wherein the vertical structure comprises: A plurality of pillar structures extending in the stacking direction and arranged along a first direction intersecting the stacking direction.
5. 5. The memory device of claim 2, wherein the vertical structure comprises a plate extending along a first direction that intersects the stacking direction.
6. 6. The memory device of claim 1, wherein the test electrodes are symmetrically arranged with respect to a center of the chip area surrounded by the chip protector.
7. 7. The memory device of claim 1, wherein, A first one of the test electrodes is coupled to the chip protector, and A second test electrode of the test electrodes is coupled from the first test electrode to the chip protector across the chip area.
8. 8. The memory device of claim 1, wherein the test electrode extends from the chip protector into the chip area.
9. 9. The memory device of claim 1, the memory device further comprising: a test circuit connected to the test electrode, Wherein the test circuit determines whether a defect has occurred in the laminate using an electrical signal input to the chip protector.
10. 10. The memory device of claim 9, wherein the test circuit uses resistance gradient information obtained by the test electrode to determine whether a defect has occurred in the stack.
11. 11. The memory device of claim 1, the memory device further comprising: and the detection circuit is arranged between the chip area and the chip protection piece.
12. 12. The memory device of claim 11, wherein the detection circuit comprises: At least one upper test line and at least one upper test plug, the at least one upper test line and the at least one upper test plug being located above the laminate, and At least one lower detection line and at least one lower detection plug, the at least one lower detection line and the at least one lower detection plug being located below the laminate.
13. 13. The memory device of claim 11, wherein the detection circuit does not penetrate the stack.
14. 14. The memory device of claim 1, the memory device further comprising: A unit plug penetrating the laminated body in the chip region, and Contacts coupled to the conductive layers in the chip region, respectively.
15. 15. The memory device of claim 14, the memory device further comprising: the semiconductor layer is formed of a semiconductor layer, the semiconductor layer is under the laminate, Wherein the unit plug contacts the semiconductor layer.
16. 16. A method of manufacturing a memory device, the method comprising the steps of: Forming a laminate in which a sacrificial layer and an interlayer insulating layer are alternately laminated; forming a first set of openings and a second set of openings through the laminate; forming a unit plug filling the first set of openings; forming a vertical structure filling the second set of openings; replacing the sacrificial layer with a conductive layer; Forming a chip protector, wherein the chip protector comprises the vertical structure; forming a test electrode electrically connected to the chip protector and the test circuit, Wherein the test circuit determines whether a defect has occurred in the laminate using an electrical signal input to the chip protector through the test electrode.
17. 17. The method of claim 16, further comprising the step of, prior to forming the laminate, Forming a lower insulating layer, and At least one lower line and at least one lower plug surrounded by the lower insulating layer are formed.
18. 18. The method of claim 17, wherein the step of forming the vertical structure comprises the steps of: The vertical structure is formed to be coupled to the at least one lower line and the at least one lower plug.
19. 19. The method of claim 16, further comprising the step of, prior to forming the test electrode, Forming an upper insulating layer on the laminate, and At least one upper line and at least one upper plug surrounded by the upper insulating layer are formed.
20. 20. The method of claim 16, wherein the step of forming the test electrode comprises the steps of: The test electrodes are formed to be spaced apart from each other, wherein the unit plugs are disposed between the test electrodes.

Description

Memory device and method of manufacturing the same Technical Field Various embodiments of the present disclosure relate to a memory device and a method of manufacturing the same, and more particularly, to a memory device including a memory block having a three-dimensional (3D) structure and a method of manufacturing the same. Background Through the semiconductor integration process, a plurality of chip regions may be formed on the semiconductor substrate. The plurality of chip regions may be distinguished from each other by using scribe line regions as boundaries. The chip regions are separated from each other by a dicing process, and thus a plurality of semiconductor chips can be manufactured. Each semiconductor chip may include a nonvolatile memory device that can hold stored data even when supplied power is interrupted. Non-volatile memory devices may be classified as two-dimensional (2D) structures or three-dimensional (3D) structures according to the structure in which the memory cells are arranged. The memory cells of the nonvolatile memory device having the 2D structure may be arranged in a single layer on the substrate, and the memory cells of the nonvolatile memory device having the 3D structure may be vertically stacked on the substrate. Since the integration of the nonvolatile memory device having the 3D structure is higher than that of the nonvolatile memory device having the 2D structure, the number of electronic devices using the nonvolatile memory device having the 3D structure has recently increased. Disclosure of Invention According to an embodiment of the present disclosure, a memory device may include a laminate in which conductive layers and interlayer insulating layers are alternately laminated in a lamination direction, a chip protector surrounding a chip region of the laminate, the chip protector penetrating the laminate in the lamination direction, and a test electrode electrically coupled to the chip protector. The test electrodes are spaced apart from each other and at least a portion of the chip area is disposed between the test electrodes. According to an embodiment of the present disclosure, a method of manufacturing a memory device may include forming a stack in which a sacrificial layer and an interlayer insulating layer are alternately stacked, forming a first group of openings and a second group of openings through the stack, forming a cell plug filling the first group of openings, forming a vertical structure filling the second group of openings, replacing the sacrificial layer with a conductive layer, forming a chip protector, wherein the chip protector includes the vertical structure, forming a test electrode electrically connected to the chip protector and a test circuit, wherein the test circuit is configured to determine whether a defect has occurred in the stack using an electrical signal input to the chip protector through the test electrode. Drawings Fig. 1 shows a diagram illustrating a structure of a memory device according to an embodiment of the present disclosure. Fig. 2A and 2B illustrate diagrams for describing a memory device including a chip protector according to the present disclosure. Fig. 3A, 3B, and 3C show diagrams illustrating arrangements of test electrodes and planar shapes of chip protectors according to various embodiments of the present disclosure. Fig. 4A and 4B show diagrams for describing a memory device including a chip protector and a detection circuit according to the present disclosure. Fig. 5A and 5B illustrate diagrams for describing a memory device including a chip protector and a memory cell array according to the present disclosure. Fig. 6A, 6B, 6C, 6D, and 6E illustrate diagrams for describing a method of manufacturing a memory device including a chip protector according to the present disclosure. Fig. 7 is a diagram illustrating a memory card system to which a memory device according to the present disclosure is applied. Fig. 8 is a diagram illustrating a Solid State Drive (SSD) system to which a memory device according to the present disclosure is applied. Detailed Description Specific structural or functional descriptions in the embodiments of the present disclosure introduced in the present specification or the present application are provided as examples describing embodiments according to the concepts of the present disclosure. Embodiments of the concepts according to the present disclosure may be practiced in various forms and should not be construed as limited to the embodiments described in the present specification or the present application. Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings, in which the embodiments of the present disclosure are shown so that those skilled in the art to which the present disclosure pertains may practice the technical spirit of the present disclosure. Some embodiments of the present disclosure relate to a memory d