CN-122028430-A - Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system including the semiconductor device are provided. The semiconductor device according to the present disclosure may include a peripheral circuit structure including a substrate and a circuit element, the substrate having a first region and a second region, the circuit element being disposed on the substrate, the first region and the second region being arranged in a first direction, and a cell structure including a mold insulating layer and a gate electrode alternately stacked, a channel structure penetrating the mold structure in the first region, a contact structure contacting the gate electrode in the second region, an upper wiring extending in a second direction crossing the first direction, the upper wiring being spaced apart from each other on the mold structure in the first direction, and a mark pattern overlapping the upper wiring in a third direction crossing the first direction and the second direction.

Inventors

• Pu Bingkun
• PU JUNFAN
• SHEN YONGJUN
• WU SHOUZHI
• WU XUANXI
• Yin Taishou
• LI XIUYING

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250527

Priority Date

20241104

Claims (20)

1. 1. A semiconductor device, comprising: a peripheral circuit structure including a substrate having a first region and a second region, and a circuit element disposed on the substrate in a first direction, and The cell structure, on the peripheral circuit structure, The unit structure comprises: a mold structure including mold insulating layers and gate electrodes alternately stacked; a channel structure through-molded in the first region; A contact structure in contact with the gate electrode in the second region; An upper wiring extending in a second direction intersecting the first direction, and The mark pattern overlaps the upper wiring in a third direction crossing the first direction and the second direction.
2. 2. The semiconductor device according to claim 1, wherein the mark pattern overlaps with the upper wiring in the first direction and the second direction.
3. 3. The semiconductor device according to claim 2, wherein an upper surface of the mark pattern is at the same height as an upper surface of the upper wiring.
4. 4. The semiconductor device according to claim 2, wherein a width of the upper surface of the mark pattern in the first direction is larger than a width of the lower surface of the mark pattern in the first direction.
5. 5. The semiconductor device according to claim 1, wherein, The upper wiring includes a first upper wiring and a second upper wiring spaced apart from the first upper wiring in a first direction, an The marking pattern includes: A first unit pattern including a first mark overlapping the first upper wiring in a third direction and a second mark overlapping the second upper wiring in the third direction, wherein the first mark and the second mark are alternately positioned in the first direction, and The second unit pattern includes a third mark overlapping the first mark in the first direction and a fourth mark overlapping the second mark in the first direction.
6. 6. The semiconductor device according to claim 5, wherein the first cell pattern and the second cell pattern are repeated in the first direction or the second direction.
7. 7. The semiconductor device according to claim 5, wherein the mark pattern further comprises an extended mark pattern which overlaps at least a portion of the first cell pattern or at least a portion of the second cell pattern in the first direction and is in the second region.
8. 8. The semiconductor device according to claim 7, wherein, The first unit pattern includes a first reference mark at one end and a second reference mark at the other end in the second direction, and The extended mark pattern includes: A first extension mark overlapping the first reference mark in a first direction; a second extension mark overlapping the second reference mark in the first direction, and And a third extension mark intermediate between the first extension mark and the second extension mark in the second direction.
9. 9. The semiconductor device according to any one of claims 1 to 8, further comprising a plurality of word line cutting structures extending in the first direction in the first region and the second region and separating the plurality of unit blocks, Wherein at least a portion of the marking pattern overlaps the word line cutting structure in a third direction.
10. 10. The semiconductor device according to claim 5, wherein the mark pattern comprises a zigzag pattern in a plan view.
11. 11. The semiconductor device according to any one of claims 1 to 8, further comprising an interlayer insulating film at a height higher than the upper wiring, Wherein the marking pattern overlaps the interlayer insulating film in the first direction and the second direction.
12. 12. The semiconductor device according to claim 11, wherein the marking pattern comprises a metallic material.
13. 13. The semiconductor device according to any one of claims 1 to 8, wherein the peripheral circuit structure includes a first bonding metal layer electrically connected to the channel structure, and the cell structure includes a second bonding metal layer in contact with the first bonding metal layer.
14. 14. The semiconductor device according to claim 13, further comprising: a board layer including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface and disposed on the upper surface of the molded structure, and The via structures are spaced apart from each other in a first direction and on the second surface of the ply, Wherein the upper wiring is on an upper surface of the via structure.
15. 15. A semiconductor device, comprising: a peripheral circuit structure including a substrate having a first region and a second region, and a circuit element disposed on the substrate in a first direction, and The cell structure, on the peripheral circuit structure, Wherein, the unit structure comprises that, A mold structure including mold insulating layers and gate electrodes alternately stacked; a channel structure through-molded in the first region; A contact structure in contact with the gate electrode in the second region; a plurality of upper wirings including an upper cell wiring in a first region and an upper extension wiring in a second region, extending in a second direction crossing the first direction and spaced apart from each other in the first direction, and A mark pattern including a unit mark pattern overlapping the unit upper wiring in a third direction crossing the first direction and the second direction and an extended mark pattern overlapping the extended upper wiring, and The extended mark pattern overlaps at least a portion of the unit mark pattern in a first direction.
16. 16. The semiconductor device according to claim 15, wherein the mark pattern overlaps the plurality of upper wirings in the first direction and the second direction, and comprises an insulating material.
17. 17. The semiconductor device according to claim 16, wherein a unit mark pattern overlaps each of upper wirings adjacent to each other among the plurality of upper wirings in the second direction.
18. 18. The semiconductor device according to claim 15, wherein each of the plurality of marks forming the mark pattern has a length in the second direction longer than a length in the first direction.
19. 19. The semiconductor device according to claim 15, wherein a length of the upper wiring on the extension in the first direction is longer than a length of the upper wiring on the cell in the first direction.
20. 20. An electronic system, comprising: A main substrate; A semiconductor device including a peripheral circuit structure and a unit structure on the stacked peripheral circuit structure and on a main substrate, and A controller electrically connected to the semiconductor device and on the main substrate, The unit structure comprises: A mold structure including a plurality of mold insulating layers and a plurality of gate electrodes alternately stacked, the plurality of mold insulating layers and the plurality of gate electrodes extending in a first direction; a channel structure through-molded in the first region; A contact structure contacting the gate electrode in the second region; an upper wiring including an upper wiring for a cell in a first region and an upper wiring for extension in a second region, the upper wiring extending in a second direction crossing the first direction, and A mark pattern including a unit mark pattern overlapping the unit upper wiring in a third direction crossing the first direction and the second direction and an extended mark pattern overlapping the extended upper wiring, and The extended mark pattern overlaps at least a portion of the unit mark pattern in a first direction.

Description

Semiconductor device and electronic system including the same Technical Field The present disclosure relates to a semiconductor device and an electronic system including the semiconductor device. Background Semiconductor devices are key components for controlling or amplifying electrical signals of electronic devices, and various types of semiconductor devices can be manufactured. Semiconductor devices may be fabricated by forming various microstructures on a semiconductor wafer through a number of unit processes, such as etching processes, deposition processes, or ion implantation processes. Further, it is desirable to check whether a defect, a position of the defect, or the like has occurred after the semiconductor device has been manufactured. In order to analyze defects of a semiconductor device, an optical apparatus (such as an electron microscope) may be used to observe the semiconductor device. In particular, in order to quickly determine where defects have occurred, etc., the location of the defects may be relatively determined based on some of the plurality of structures of the semiconductor device. Disclosure of Invention The present disclosure has been made in an effort to provide a semiconductor device including a marking pattern that facilitates determination of a location of a defect. According to some example embodiments of the present disclosure for solving the above-mentioned technical problems, a semiconductor device includes a peripheral circuit structure including a substrate having a first region and a second region, and a circuit element on the substrate, the first region and the second region being arranged in a first direction, and a cell structure on the peripheral circuit structure. The cell structure includes a mold structure including mold insulating layers and gate electrodes alternately stacked, a channel structure penetrating the mold structure in a first region, a contact structure contacting the gate electrodes in a second region, an upper wiring extending in a second direction crossing the first direction, and a mark pattern overlapping the upper wiring in a third direction crossing the first direction and the second direction. According to some example embodiments of the present disclosure for solving the above-mentioned technical problems, a semiconductor device includes a peripheral circuit structure including a substrate having a first region and a second region arranged side by side in a first direction, and a circuit element on the substrate, the first region and the second region being in the first direction, and a cell structure on the peripheral circuit structure. The cell structure includes a molding structure including a molding insulating layer and a gate electrode alternately stacked, a channel structure penetrating the molding structure in a first region, a contact structure contacting the gate electrode in a second region, a plurality of upper wirings including an upper cell wiring in the first region and an upper extension wiring in the second region, extending in a second direction crossing the first direction and spaced apart from each other in the first direction, and a marking pattern including a cell marking pattern and an extension marking pattern, the cell marking pattern overlapping the upper cell wiring in a third direction crossing the first direction and the second direction, the extension marking pattern overlapping the upper extension wiring. The extended mark pattern overlaps at least a portion of the unit mark pattern in a first direction. According to some example embodiments of the present disclosure for solving the above-mentioned technical problems, an electronic system includes a main substrate, a semiconductor device including a peripheral circuit structure and a unit structure on the stacked peripheral circuit structures on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate. The cell structure includes a mold structure including a plurality of mold insulating layers and a plurality of gate electrodes alternately stacked, the plurality of mold insulating layers and the plurality of gate electrodes extending in a first direction, a channel structure penetrating the mold structure in a first region, a contact structure contacting the gate electrodes in a second region, an upper wiring including an upper cell wiring in the first region and an upper extension wiring in the second region extending in a second direction crossing the first direction, and a mark pattern including a cell mark pattern and an extension mark pattern, the cell mark pattern overlapping the upper cell wiring in a third direction crossing the first direction and the second direction, the extension mark pattern overlapping the upper extension wiring. The extended mark pattern overlaps at least a portion of the unit mark pattern in a first direction. According to some example embodiments of the present disclosure