CN-122028433-A - Memory architecture with bipolar semiconductor channel

Abstract

The present application relates to a memory architecture having bipolar semiconductor channels. The memory device may include a plurality of conductors each associated with a respective activation line of the memory array, and a pillar extending through the conductors. The pillars may include semiconductor material extending along a length of the pillars and associated with bipolar channels along the length of the pillars. The memory device may also include a plurality of storage portions (e.g., for storing charge, dipole polarization, or a combination thereof) each including one or more storage materials. Each storage portion may be associated with a respective memory cell of the memory array and may be positioned along the length of the pillar between a respective one of the conductors and a respective portion of the semiconductor material.

Inventors

• FANTINI PIERO
• I. Toltorelli
• A. Pirovano
• M. Faronato
• IELMINI DANIELE

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20251112

Priority Date

20251029

Claims (20)

1. 1. A memory device, comprising: a plurality of conductors distributed along a direction from a substrate of the memory device, each of the plurality of conductors associated with a respective one of a plurality of activation lines of a memory array; a pillar extending from the substrate in the direction through the plurality of conductors, the pillar comprising a semiconductor material extending along a length of the pillar and associated with a bipolar channel along the length of the pillar, and A plurality of storage portions, each of the plurality of storage portions associated with a respective memory cell of the memory array and including one or more storage materials positioned between a respective one of the plurality of conductors and a respective portion of the semiconductor material along the length of the pillar.
2. 2. The memory device of claim 1, wherein a conductivity of the bipolar channel is above a threshold conductivity in response to an activation voltage being below a first threshold voltage, below the threshold conductivity in response to an activation voltage being between the first threshold voltage and a second threshold voltage, and above the threshold conductivity in response to an activation voltage being above the second threshold voltage.
3. 3. The memory device of claim 1, wherein the semiconductor material comprises a transition metal disulfide material.
4. 4. The memory device of claim 1, wherein each of the plurality of storage portions comprises a ferroelectric material, a charge trapping material, or a combination thereof.
5. 5. The memory device of claim 4, wherein each respective memory cell is operable to store a respective logic state based at least in part on charge stored in a respective portion of the charge trapping material of the one or more storage materials, dipole polarization stored in a respective portion of the ferroelectric material of the one or more storage materials, or a combination thereof.
6. 6. The memory device of claim 1, wherein the one or more storage materials are included in a continuous composition of the one or more storage materials around the semiconductor material.
7. 7. The memory device of claim 1, wherein the semiconductor material is a layer of semiconductor material around a dielectric core of the pillars.
8. 8. The memory device of claim 1, wherein, for each of the plurality of storage portions, a storage material of the one or more storage materials is in contact with a respective portion of the semiconductor material.
9. 9. The memory device of claim 1, further comprising: One or more dielectric materials positioned between the plurality of conductors and the plurality of storage portions.
10. 10. The memory device of claim 1, further comprising: A first select line operable to couple a first end of the pillar with a first access line of the memory array, an A second select line operable to couple a second end of the pillar with a second access line of the memory array.
11. 11. A method for operating a memory device, comprising: Writing a logic state to a memory cell of a memory array, wherein the writing comprises: Biasing a pillar associated with a bipolar semiconductor channel extending through a plurality of activation lines of the memory array along a length of the pillar with a first voltage; Biasing a first active line of the plurality of active lines with a second voltage less than the first voltage, the first active line coupled with the memory cell; Biasing one or more second active lines of the plurality of active lines other than the first active line with a third voltage different from the first voltage and the second voltage, and The electric field is stored in one or more memory materials positioned between the first active line and the bipolar semiconductor channel based at least in part on biasing the pillar with the first voltage, biasing the first active line with the second voltage, and biasing the one or more second active lines with the third voltage.
12. 12. The method according to claim 11, wherein: Biasing the first activation line with the second voltage less than the first voltage is configured to activate a first portion of the bipolar semiconductor channel, and The one or more second activation lines are biased with the third voltage different from the first voltage and the second voltage configured to activate one or more second portions of the bipolar semiconductor channel.
13. 13. The method of claim 11, wherein an absolute difference between the second voltage and the first voltage is greater than an absolute difference between the third voltage and the first voltage.
14. 14. The method of claim 11, wherein the third voltage is between the first voltage and the second voltage.
15. 15. The method of claim 11, wherein biasing the pillar with the first voltage is based at least in part on coupling the pillar with an access line of the memory array biased with the first voltage.
16. 16. The method of claim 15, wherein the access line is coupled with a first end of the pillar, the method further comprising: A second end of the pillar is isolated from a second access line of the memory array when the pillar is coupled with an access line.
17. 17. The method as recited in claim 16, further comprising: Isolating a first end of a second pillar from the access line during the writing, the second pillar associated with a second bipolar semiconductor channel extending through the plurality of activation lines along a length of the second pillar, and A second end of the second pillar is isolated from the second access line during the writing.
18. 18. The method as recited in claim 11, further comprising: Erasing the memory cell, wherein the erasing comprises: biasing the strut with the first voltage; Biasing the first active line with a fourth voltage greater than the first voltage; biasing the one or more second active lines with a fifth voltage different from the first voltage and the fourth voltage, and A second electric field is stored in the one or more memory materials based at least in part on biasing the pillar with the first voltage, biasing the first activation line with the fourth voltage, and biasing the one or more second activation lines with the fifth voltage.
19. 19. The method according to claim 18, wherein: biasing the first activation line with the fourth voltage greater than the first voltage is configured to activate a first portion of the bipolar semiconductor channel, and The one or more second activation lines are biased with the fifth voltage different from the first voltage and the fourth voltage configured to activate one or more second portions of the bipolar semiconductor channel.
20. 20. The method of claim 18, wherein an absolute difference between the fourth voltage and the first voltage is greater than an absolute difference between the fifth voltage and the first voltage.

Description

Memory architecture with bipolar semiconductor channel Cross reference to This patent application claims priority from U.S. patent application No. 19/373,387 entitled "memory architecture with bipolar semiconductor channel (MEMORY ARCHITECTURES WITH AMBIPOLAR SEMICONDUCTOR CHANNELS)" filed by Van Dinni (Fantini) et al at 2025, 10, 29, which claims priority from U.S. patent application No. 63/719,503 entitled "memory architecture with bipolar semiconductor channel (MEMORY ARCHITECTURES WITH AMBIPOLAR SEMICONDUCTOR CHANNELS)" filed by Van Dinni (Fantini) et al at 2024, 11, 12, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field The technical field relates to one or more systems for memory, including memory architectures having bipolar semiconductor channels. Background Memory devices are widely used to store information in a variety of electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two support states, typically corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any of which may be stored by the memory cell. To access information stored by the memory device, the component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component can write (e.g., program, set, assign) one or more memory cells within a memory device to a corresponding state. There are various types of memory devices including magnetic hard disks, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), synchronous Dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase Change Memory (PCM), three-dimensional cross point memory (3D cross point), NOR and NAND memory devices, and others. The memory device may be described in terms of a volatile configuration or a non-volatile configuration. Volatile memory cells (e.g., DRAMs) lose their programmed state over time unless they are periodically refreshed by an external power source. Nonvolatile memory cells (e.g., NAND) can maintain their programmed state for long periods of time even in the absence of external power. Disclosure of Invention A memory device is described. The memory device may include a plurality of conductors distributed along a direction from a substrate of the memory device, each of the plurality of conductors being associated with a respective one of a plurality of activation lines of a memory array, a pillar extending from the substrate along the direction through the plurality of conductors, the pillar including a semiconductor material extending along a length of the pillar and being associated with a bipolar channel along the length of the pillar, and a plurality of storage portions, each of the plurality of storage portions being associated with a respective memory cell of the memory array and including one or more storage materials positioned between a respective one of the plurality of conductors and a respective portion of the semiconductor material along the length of the pillar. A method for operating a memory device is described. The method for operating a memory device may include writing a logic state to a memory cell of a memory array, wherein the writing includes biasing a pillar with a first voltage, the pillar associated with a bipolar semiconductor channel extending through a plurality of active lines of the memory array along a length of the pillar, biasing a first active line of the plurality of active lines with a second voltage less than the first voltage, the first active line coupled with the memory cell, biasing one or more second active lines of the plurality of active lines other than the first active line with a third voltage different from the first voltage and the second voltage, and storing an electric field in one or more storage materials positioned between the first active line and the bipolar semiconductor channel based at least in part on biasing the pillar with the first voltage, biasing the first active line with the second voltage, and biasing the one or more second active lines with the third voltage. A memory device is described. The memory device may include one or more memory arrays and circuitry coupled with the one or more memory arrays and configured to cause the memory device to write a logic state to memory cells of the memory arrays of the one or more memory arrays, wherein the writing includes biasing a pillar with a first voltage, the pillar being associated with a bipolar semiconductor channel extending through a plurality of active lines of the memo