CN-122028434-A - Semiconductor device, manufacturing method and control method thereof

Abstract

The application provides a semiconductor device, a manufacturing method and a control method thereof, wherein the manufacturing method comprises providing a substrate on which a transistor is formed; and forming a first capacitor and a second capacitor connected in parallel with each other on the first dielectric layer, wherein the first capacitor comprises a first top electrode layer, a first capacitor dielectric layer and a first bottom electrode layer, the second capacitor comprises a second top electrode layer, a second capacitor dielectric layer and a second bottom electrode layer, the first bottom electrode layer and the second bottom electrode layer are electrically connected with the transistor, and the thicknesses of the first capacitor dielectric layer and the second capacitor dielectric layer are different. According to the application, two capacitors connected in parallel are formed on the dielectric layer, and different capacitors have different coercive electric fields due to different thicknesses of the dielectric layers of the capacitors, so that a plurality of different storage states are realized in one storage unit, and the storage capacity of the device is improved.

Inventors

• LI HONGBO
• YANG XIAOFANG
• JIN XINGCHENG

Assignees

• 无锡华润微电子有限公司

Dates

Publication Date

20260512

Application Date

20241108

Claims (10)

1. 1. A method of manufacturing a semiconductor device, comprising: providing a substrate, wherein a transistor is formed on the substrate; forming a first dielectric layer covering the transistor; and forming a first capacitor and a second capacitor which are connected in parallel with each other on the first dielectric layer, wherein the first capacitor comprises a first top electrode layer, a first capacitor dielectric layer and a first bottom electrode layer, the second capacitor comprises a second top electrode layer, a second capacitor dielectric layer and a second bottom electrode layer, the first bottom electrode layer and the second bottom electrode layer are electrically connected with the transistor, and the thicknesses of the first capacitor dielectric layer and the second capacitor dielectric layer are different.
2. 2. The method of manufacturing of claim 1, wherein a first conductive plug and a second conductive plug are formed in the first dielectric layer, wherein the first conductive plug electrically connects the first bottom electrode layer and the drain of the transistor, and wherein the second conductive plug electrically connects the second bottom electrode layer and the drain of the transistor.
3. 3. The method of manufacturing of claim 2, wherein forming the first capacitor and the second capacitor connected in parallel with each other on the first dielectric layer comprises: sequentially forming a first bottom electrode material layer, a first capacitance dielectric material layer and a first top electrode material layer on the first dielectric layer; Patterning the first top electrode material layer, the first capacitance dielectric material layer and the first bottom electrode material layer to form the first capacitance, wherein the first capacitance comprises a first top electrode layer, a first capacitance dielectric layer and a first bottom electrode layer; Sequentially forming a second bottom electrode material layer, a second capacitance dielectric material layer and a second top electrode material layer on the first dielectric layer; and patterning the second top electrode material layer, the second capacitance dielectric material layer and the second bottom electrode material layer to form the second capacitor, wherein the second capacitor comprises a second top electrode layer, a second capacitance dielectric layer and a second bottom electrode layer.
4. 4. A method of manufacturing as claimed in claim 3, wherein the method further comprises: Forming a second dielectric layer covering the first dielectric layer, the first capacitor and the second capacitor; And forming a third conductive plug and a fourth conductive plug in the second dielectric layer, wherein the third conductive plug is electrically connected with the first top electrode layer, and the fourth conductive plug is electrically connected with the second top electrode layer.
5. 5. The method of manufacturing of claim 4, further comprising, after forming the third conductive plug and the fourth conductive plug: And forming a first conductive layer on the second dielectric layer, wherein the first conductive layer is electrically connected with the third conductive plug and the fourth conductive plug.
6. 6. The method of manufacturing of claim 1, wherein the first capacitive dielectric layer has a thickness of 6nm to 10nm, the second capacitive dielectric layer has a thickness of 16nm to 20nm, and the first capacitive dielectric layer and the second capacitive dielectric layer comprise ferroelectric materials.
7. 7. A semiconductor device, comprising: A substrate; A transistor on the substrate; a first dielectric layer on the substrate and covering the transistor; And the first capacitor and the second capacitor are arranged on the first dielectric layer and connected in parallel, wherein the first capacitor comprises a first top electrode layer, a first capacitor dielectric layer and a first bottom electrode layer, the second capacitor comprises a second top electrode layer, a second capacitor dielectric layer and a second bottom electrode layer, the first bottom electrode layer and the second bottom electrode layer are electrically connected with the transistor, and the thicknesses of the first capacitor dielectric layer and the second capacitor dielectric layer are different.
8. 8. The semiconductor device according to claim 7, wherein a first conductive plug and a second conductive plug are formed in the first dielectric layer, wherein the first conductive plug electrically connects the first bottom electrode layer and a drain of the transistor, and wherein the second conductive plug electrically connects the second bottom electrode layer and the drain of the transistor.
9. 9. The semiconductor device of claim 8, further comprising a second dielectric layer covering the first dielectric layer, the first capacitor, and the second capacitor, wherein a third conductive plug and a fourth conductive plug are formed in the second dielectric layer, wherein the third conductive plug is electrically connected to the first top electrode layer, the fourth conductive plug is electrically connected to the second top electrode layer, and a first conductive layer is formed on the second dielectric layer, wherein the first conductive layer is electrically connected to the third conductive plug and the fourth conductive plug.
10. 10. A control method of the semiconductor device according to any one of claims 7 to 9, comprising: acquiring a writing voltage of the semiconductor device; A memory state of the semiconductor device is determined based on a relationship of the write voltage to coercive electric fields of a first capacitance and a second capacitance, the memory state of the semiconductor device being characterized by logic states of the first capacitance and the second capacitance in parallel.

Description

Semiconductor device, manufacturing method and control method thereof Technical Field The application relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method and a control method thereof. Background The ferroelectric Memory (Ferromagnetic RandomAccess Memory, feRAM) is a new type of Memory, has both the non-volatility of Read-Only Memory (ROM) and the non-volatility of random access Memory (RandomAccess Memory, RAM), and has the advantages of high-speed reading and writing, high durability, low power consumption, high uniformity, radiation resistance, etc., and is widely used in the fields of automotive electronics, industry, aerospace, etc. In the related art, a 1T1C memory structure is adopted as a ferroelectric memory, and a memory cell of the 1T1C memory structure includes a Transistor (T) and a ferroelectric Capacitor (C). The ferroelectric capacitor adopts a Metal-ferroelectric-Metal (MFM) structure, namely, a Hafnium Zirconium Oxide (HZO) ferroelectric film material is arranged between two layers of Metal electrodes. The HZO ferroelectric film has spontaneous polarization characteristics, and can generate spontaneous polarization steering under the action of an external electric field applied by the upper electrode and the lower electrode of the metal, but the current ferroelectric memory can only switch in two polarization states, namely can only realize 1-bit memory in one memory unit, and has smaller memory capacity. Disclosure of Invention In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the application is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In order to solve the problems existing at present, one aspect of the application provides a manufacturing method of a semiconductor device, which comprises the steps of providing a substrate, forming a transistor on the substrate, forming a first dielectric layer covering the transistor, and forming a first capacitor and a second capacitor which are connected in parallel on the first dielectric layer, wherein the first capacitor comprises a first top electrode layer, a first capacitor dielectric layer and a first bottom electrode layer, the second capacitor comprises a second top electrode layer, a second capacitor dielectric layer and a second bottom electrode layer, the first bottom electrode layer and the second bottom electrode layer are electrically connected with the transistor, and the thicknesses of the first capacitor dielectric layer and the second capacitor dielectric layer are different. Illustratively, a first conductive plug and a second conductive plug are formed in the first dielectric layer, wherein the first conductive plug electrically connects the first bottom electrode layer and the drain of the transistor, and the second conductive plug electrically connects the second bottom electrode layer and the drain of the transistor. The method for forming the first capacitor and the second capacitor on the first dielectric layer in parallel comprises the steps of sequentially forming a first bottom electrode material layer, a first capacitor dielectric material layer and a first top electrode material layer on the first dielectric layer, patterning the first top electrode material layer, the first capacitor dielectric material layer and the first bottom electrode material layer to form the first capacitor, wherein the first capacitor comprises a first top electrode layer, a first capacitor dielectric layer and a first bottom electrode layer, sequentially forming a second bottom electrode material layer, a second capacitor dielectric material layer and a second top electrode material layer on the first dielectric layer, and patterning the second top electrode material layer, the second capacitor dielectric material layer and the second bottom electrode material layer to form the second capacitor, and the second capacitor comprises a second top electrode layer, a second capacitor dielectric layer and a second bottom electrode layer. The method further includes forming a second dielectric layer overlying the first dielectric layer, the first capacitor, and the second capacitor, and forming third and fourth conductive plugs in the second dielectric layer, wherein the third conductive plug is electrically connected to the first top electrode layer and the fourth conductive plug is electrically connected to the second top electrode layer. Illustratively, after forming the third conductive plug and the fourth conductive plug, forming a first conductive layer on the second dielectric layer, wherein the first conductive layer is electrically connected to the third conductive plug and the fourth conductive plug. Illustratively, the thickn