CN-122028436-A - Memory cell, memristor structure, preparation method of memristor structure and data reading method of memristor structure

CN122028436ACN 122028436 ACN122028436 ACN 122028436ACN-122028436-A

Abstract

The invention provides a memory cell, a memristor structure, a preparation method thereof and a data reading method, wherein the memory cell comprises a substrate, a bottom electrode, a functional layer, a phase change oxide layer and a top electrode, wherein the bottom electrode is positioned on the surface of the substrate, the functional layer is positioned on the surface of the bottom electrode, the phase change oxide layer is positioned on the surface of the functional layer, the phase change oxide layer is made of vanadium oxide or niobium oxide, and the top electrode is positioned on the surface of the phase change oxide layer. Based on the threshold switching characteristics of the phase change oxide layer, there is a downward abrupt change in the current of the memory cell when the read voltage is changed toward the 1/2 read voltage, so that the current of the memory cell at the 1/2 read voltage is reduced, i.e., the undercurrent current is reduced.

Inventors

WANG CHEN
CAI BINGQI
CHEN KUN
CHEN LIN
SUN QINGQING
ZHANG WEI

Assignees

复旦大学
嘉善复旦研究院

Dates

Publication Date: 20260512
Application Date: 20260119

Claims (10)

1. A memory cell, comprising: A substrate; A bottom electrode located on the surface of the substrate; The functional layer is positioned on the surface of the bottom electrode; The phase change oxide layer is positioned on the surface of the functional layer, and the phase change oxide layer is made of vanadium oxide or niobium oxide; And the top electrode is positioned on the surface of the phase-change oxide layer.
2. The memory cell of claim 1 wherein the bottom electrode and the top electrode are the same material, the bottom electrode being of a metal material having a high work function.
3. The memory cell of claim 1 wherein the phase change oxide layer has a thickness of less than 10nm.
4. The memory cell of claim 1, wherein the area of the memory cell projected perpendicularly onto the substrate is in the range of 25 μm 2 ~100μm 2 .
5. The memory cell of claim 1, wherein the functional layer is an insulating oxide and the substrate is a silicon substrate or a silicon oxide substrate.
6. A memristor structure, which comprises a first substrate and a second substrate, characterized by comprising the following steps: A substrate; The first metal layers are located on the surface of the substrate at intervals along the first direction, the extending direction of the first metal layers is a second direction, and the first direction and the second direction are parallel to the surface of the substrate and perpendicular to each other; the functional layer is positioned on the surfaces of the substrate and the first metal layer; The phase change oxide layer is positioned on the surface of the functional layer, and the phase change oxide layer is made of vanadium oxide or niobium oxide; The second metal layers are distributed at intervals along the second direction and are positioned on the surface of the phase change oxide layer, and the extending direction of the second metal layers is the first direction; Wherein, the part of the first metal layer corresponding to the upper and lower parts of the second metal layer is a bottom electrode, the part of the second metal layer corresponding to the upper and lower parts of the first metal layer is a top electrode, the bottom electrode, the top electrode, the functional layer and the phase change oxide layer between the bottom electrode and the top electrode form a memory cell, and the substrate is provided with a memory cell array formed by a plurality of memory cells distributed in an array.
7. A method of fabricating a memristor structure, comprising: Providing a substrate; Forming a plurality of first metal layers which are distributed at intervals along a first direction on the substrate, wherein the first metal layers are positioned on the surface of the substrate, the extending direction of the first metal layers is a second direction, and the first direction and the second direction are parallel to the surface of the substrate and are mutually perpendicular; Forming a functional layer on the surface of the first metal layer and the surface of the substrate; Forming a phase change oxide layer on the surface of the functional layer, wherein the phase change oxide layer is made of vanadium oxide or niobium oxide; Forming a plurality of second metal layers which are distributed at intervals along the second direction on the phase change oxide layer, wherein the extending direction of the second metal layers is the first direction; Wherein, the part of the first metal layer corresponding to the upper and lower parts of the second metal layer is a bottom electrode, the part of the second metal layer corresponding to the upper and lower parts of the first metal layer is a top electrode, the bottom electrode, the top electrode, the functional layer between the bottom electrode and the top electrode, and the phase change oxide layer constitute a memory cell.
8. The method of claim 7, wherein the forming the first metal layer, the second metal layer, the functional layer, and the phase change oxide layer is any one of magnetron sputtering, atomic layer deposition, and pulsed laser deposition.
9. The method for reading data, applied to the memristor structure as claimed in claim 6, comprises: Determining a second metal layer corresponding to a bottom electrode of a target memory cell as a target second metal layer, and determining a first metal layer corresponding to a top electrode of the target memory cell as a target first metal layer; A read voltage is applied to the target second metal layer and the target first metal layer is connected to ground while a 1/2 read voltage is applied to the first metal layer and the second metal layer except for the target first metal layer and the target second metal layer.
10. The method of claim 9, wherein the read voltage has a value ranging from 0.4v to 0.8v.

Description

Memory cell, memristor structure, preparation method of memristor structure and data reading method of memristor structure Technical Field The invention relates to the field of semiconductor devices, in particular to a memory cell, a memristor structure, a preparation method of the memory cell and a data reading method of the memristor structure. Background Resistive random access memories are commonly used in large scale integration in a crossbar array structure, where each memory cell is located at the intersection of a word line and a bit line. If there are memory cells in the array structure with low resistance, when reading or writing a certain cell, other unselected cells may form parallel paths, resulting in current leakage, which is a undercurrent problem. Referring to fig. 1, fig. 1 is a graph of dc scan current versus voltage of a memory cell, wherein the abscissa is the scan voltage and the ordinate is the scan current. In the process of changing the scanning voltage applied to the memory cell from the reading voltage V to the 1/2 reading voltage V, the change of the scanning current is small, and therefore, the undercurrent generated by the memory cell at the 1/2 reading voltage V is large. Among other things, the undercurrent can have the following effects: 1. during reading, the undercurrents can interfere with the current of the target cell, resulting in reading errors; 2. During writing, the undercurrent may falsely trigger a state change of the neighboring cells; 3. the undercurrents increase power consumption and affect energy efficiency. Disclosure of Invention The invention provides a memory cell, a memristor structure, a preparation method thereof and a data reading method thereof, so as to weaken the undercurrent effect. According to a first aspect of the present invention, there is provided a memory cell comprising: A substrate; A bottom electrode located on the surface of the substrate; The functional layer is positioned on the surface of the bottom electrode; The phase change oxide layer is positioned on the surface of the functional layer, and the phase change oxide layer is made of vanadium oxide or niobium oxide; And the top electrode is positioned on the surface of the phase-change oxide layer. Optionally, the materials of the bottom electrode and the top electrode are the same, and the material of the bottom electrode is a metal material with a high work function. Optionally, the thickness of the phase change oxide layer is less than 10nm. Optionally, an area of the vertical projection of the memory cell on the substrate ranges from 25 μm 2~100μm2. Optionally, the material of the functional layer is an insulating oxide, and the substrate is a silicon substrate or a silicon oxide substrate. According to a second aspect of the present invention, there is provided a memristor structure comprising: A substrate; The first metal layers are located on the surface of the substrate at intervals along the first direction, the extending direction of the first metal layers is a second direction, and the first direction and the second direction are parallel to the surface of the substrate and perpendicular to each other; the functional layer is positioned on the surfaces of the substrate and the first metal layer; The phase change oxide layer is positioned on the surface of the functional layer, and the phase change oxide layer is made of vanadium oxide or niobium oxide; The second metal layers are distributed at intervals along the second direction and are positioned on the surface of the phase change oxide layer, and the extending direction of the second metal layers is the first direction; Wherein, the part of the first metal layer corresponding to the upper and lower parts of the second metal layer is a bottom electrode, the part of the second metal layer corresponding to the upper and lower parts of the first metal layer is a top electrode, the bottom electrode, the top electrode, the functional layer and the phase change oxide layer between the bottom electrode and the top electrode form a memory cell, and the substrate is provided with a memory cell array formed by a plurality of memory cells distributed in an array. According to a third aspect of the present invention, there is provided a method of manufacturing a memristor structure, comprising: Providing a substrate; Forming a plurality of first metal layers which are distributed at intervals along a first direction on the substrate, wherein the first metal layers are positioned on the surface of the substrate, the extending direction of the first metal layers is a second direction, and the first direction and the second direction are parallel to the surface of the substrate and are mutually perpendicular; Forming a functional layer on the surface of the first metal layer and the surface of the substrate; Forming a phase change oxide layer on the surface of the functional layer, wherein the phase change oxide layer is made of vana