CN-122028437-A - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Abstract

A semiconductor device is disclosed. The semiconductor device may include a package substrate, a plurality of semiconductor chips stacked on the package substrate and each having a first side surface, and a first conductive film electrically connected with the package substrate and extending to a region located on the first side surface of the plurality of semiconductor chips. Each of the plurality of semiconductor chips may include a peripheral circuit structure including a first bonding pad on a first surface of a substrate, a first cell array structure including a first stack and a second bonding pad bonded to the first bonding pad, and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film.

Inventors

• LI ENHUI
• LI GENRONG
• Li Renzai

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250718

Priority Date

20241106

Claims (20)

1. 1. A semiconductor device, the semiconductor device comprising: packaging a substrate; a plurality of semiconductor chips stacked on the package substrate, and each of the plurality of semiconductor chips having a first side surface; and A first conductive film electrically connected with the package substrate and extending to a region located on the first side surface of the plurality of semiconductor chips, Wherein each of the plurality of semiconductor chips includes a peripheral circuit structure including a first bonding pad on a first surface of a substrate, a first cell array structure including a first stack and a second bonding pad bonded to the first bonding pad, and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film.
2. 2. The semiconductor device according to claim 1, Wherein each of the plurality of semiconductor chips further comprises conductive contacts between the first and second bond pads and the first input/output pad, and Wherein the first input/output pad is electrically connected to the conductive contact and the first and second bond pads.
3. 3. The semiconductor device of claim 2, wherein the conductive contact is in contact with side surfaces of the first and second bond pads.
4. 4. The semiconductor device according to claim 1, Wherein the peripheral circuit structure includes a peripheral interlayer insulating layer surrounding the first bonding pad, Wherein the first cell array structure includes an interlayer insulating layer surrounding the second bonding pad, and Wherein the first input/output pads are disposed on the peripheral interlayer insulating layer and side surfaces of the interlayer insulating layer.
5. 5. The semiconductor device of claim 1, wherein the first side surfaces of the plurality of semiconductor chips are aligned with each other.
6. 6. The semiconductor device of claim 1, wherein each of the plurality of semiconductor chips further comprises a second input/output pad disposed on a second side surface thereof.
7. 7. The semiconductor device of claim 6, wherein the first side surface is opposite the second side surface.
8. 8. The semiconductor device of claim 1, wherein each of the plurality of semiconductor chips further comprises: A vertical structure penetrating the first stack, and A bit line disposed between the second bond pad and the first stack in a vertical cross section and connected to the vertical structure.
9. 9. A semiconductor device, the semiconductor device comprising: packaging a substrate; A plurality of semiconductor chips stacked on the package substrate, and each of the plurality of semiconductor chips having a first side surface; A molding layer disposed on the package substrate to surround the plurality of semiconductor chips, and A first conductive film electrically connected with the package substrate and extending to a region located on the first side surface of the plurality of semiconductor chips, Wherein each of the plurality of semiconductor chips includes a peripheral circuit structure including a first bonding pad on a first surface of a substrate and a second bonding pad on a second surface opposite the first surface, a first cell array structure including a third bonding pad bonded to the first bonding pad, and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film, The first cell array structure includes a first stack including a first insulating pattern and a first gate pattern vertically alternately stacked, a vertical structure penetrating the first stack, and a bit line electrically connected with the vertical structure.
10. 10. The semiconductor device according to claim 9, Wherein the peripheral circuit structure includes a peripheral interlayer insulating layer surrounding the first bonding pad, Wherein the first cell array structure includes an interlayer insulating layer surrounding the third bonding pad, and Wherein the first input/output pads are disposed on the peripheral interlayer insulating layer and side surfaces of the interlayer insulating layer.
11. 11. The semiconductor device of claim 9, further comprising: A second conductive film electrically connected to the interconnection pattern and extending to a region located on a second side surface of the semiconductor chip, Wherein each of the plurality of semiconductor chips further comprises: A second cell array structure including a fourth bonding pad bonded to the second bonding pad, and And second input/output pads provided on each of the second side surfaces and electrically connected to the second conductive film.
12. 12. The semiconductor device according to claim 11, Wherein the first side surfaces of the plurality of semiconductor chips are aligned with each other, and Wherein the second side surfaces of the plurality of semiconductor chips are aligned with each other.
13. 13. The semiconductor device according to claim 11, Wherein the first input/output pad is electrically connected to one of the third bond pads adjacent to the first side surface, and Wherein the second input/output pad is electrically connected to one of the fourth bond pads adjacent to the second side surface.
14. 14. The semiconductor device of claim 11, wherein the first side surface is opposite the second side surface.
15. 15. A semiconductor device, the semiconductor device comprising: a peripheral circuit structure comprising a first bond pad on a first surface of a substrate and a second bond pad on a second surface of the substrate; a first cell array structure is provided, which has a first cell array structure, the first cell array structure is opposite to the first surface; A second cell array structure having a first cell array structure, the second cell array structure is opposite to the second surface; A first input/output pad on a first side surface of the peripheral circuit structure, and A second input/output pad on a second side surface of the peripheral circuit structure, The first cell array structure includes a first stack including a first insulating pattern and a first gate pattern vertically alternately stacked, a first vertical structure penetrating the first stack, and a third bonding pad bonded with the first bonding pad, and The second cell array structure includes a second stack including a second insulating pattern and a second gate pattern vertically alternately stacked, a second vertical structure penetrating the second stack, and a fourth bonding pad bonded with the second bonding pad.
16. 16. The semiconductor device of claim 15, Wherein the first cell array structure includes a first bit line located between the first vertical structure and the third bond pad when viewed in a vertical cross section, and Wherein the second cell array structure includes a second bit line located between the second vertical structure and the fourth bond pad when viewed in the vertical cross section.
17. 17. The semiconductor device of claim 15, Wherein the first input/output pad is in contact with the first side surface of the first cell array structure, and Wherein the second input/output pad is in contact with a second side surface of the second cell array structure.
18. 18. The semiconductor device of claim 17, Wherein the first input/output pad is electrically connected to one of the third bond pads adjacent to the first side surface, and Wherein the second input/output pad is electrically connected to one of the fourth bond pads adjacent to the second side surface.
19. 19. The semiconductor device of claim 15, Wherein the peripheral circuit structure further comprises: a first peripheral interlayer insulating layer surrounding the first bonding pad, and A second peripheral interlayer insulating layer surrounding the second bonding pad, Wherein the first cell array structure further includes a first interlayer insulating layer surrounding the third bonding pad, Wherein the second cell array structure further includes a second interlayer insulating layer surrounding the fourth bonding pad, Wherein the first input/output pad is located on the first peripheral interlayer insulating layer and a side surface of the first interlayer insulating layer, and Wherein the second input/output pad is located on the second peripheral interlayer insulating layer and a side surface of the second interlayer insulating layer.
20. 20. The semiconductor device of claim 15, wherein the peripheral circuit structure further comprises: Peripheral circuitry on the first surface of the substrate, and A penetrating via pattern provided to penetrate the substrate and electrically connected with a portion of the peripheral circuit.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Technical Field The present disclosure relates to a semiconductor device and a semiconductor package including the same. Background As a data memory of an electronic system, a semiconductor device capable of storing a large amount of data is required. Accordingly, many studies are being conducted to increase the data storage capacity of the semiconductor device. For example, a semiconductor device in which memory cells are arranged three-dimensionally is proposed. In addition, a semiconductor packaging technology for integrating a semiconductor device including a memory cell in a single package is required. In the case of a semiconductor package integrating a plurality of devices, it is required to reduce the size of the semiconductor package and improve heat dissipation and electrical characteristics of the semiconductor package. Disclosure of Invention Embodiments of the inventive concept provide a semiconductor device having increased integration density. According to an embodiment of the inventive concept, a semiconductor device may include a package substrate, a plurality of semiconductor chips stacked on the package substrate and each having a first side surface, and a first conductive film electrically connected with the package substrate and extending to a region on the first side surface of the plurality of semiconductor chips. Each of the plurality of semiconductor chips may include a peripheral circuit structure including a first bonding pad on a first surface of a substrate, a first cell array structure including a first stack and a second bonding pad bonded to the first bonding pad, and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film. According to an embodiment of the inventive concept, a semiconductor device may include a package substrate, a plurality of semiconductor chips stacked on the package substrate and each having a first side surface, a molding layer disposed on the package substrate to surround the semiconductor chips, and a first conductive film electrically connected with the package substrate and extending to a region on the first side surfaces of the plurality of semiconductor chips. Each of the plurality of semiconductor chips may include a peripheral circuit structure including a first bonding pad on a first surface of a substrate and a second bonding pad on a second surface opposite the first surface, a first cell array structure including a third bonding pad bonded to the first bonding pad, and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film. The first cell array structure may include a first stack including a first insulating pattern and a first gate pattern vertically alternately stacked, a vertical structure penetrating the first stack, and a bit line electrically connected with the vertical structure. According to an embodiment of the inventive concept, a semiconductor device may include a peripheral circuit structure including a first bonding pad on a first surface of a substrate and a second bonding pad on a second surface of the substrate, and a first cell array structure opposite to the first surface, a second cell array structure opposite to the second surface, a first input/output pad on a first side surface of the peripheral circuit structure, and a second input/output pad on a second side surface of the peripheral circuit structure. The first cell array structure may include a first stack including a first insulating pattern and a first gate pattern vertically alternately stacked, a first vertical structure penetrating the first stack, and a third bonding pad bonded with the first bonding pad. The second cell array structure may include a second stack including a second insulating pattern and a second gate pattern vertically alternately stacked, a second vertical structure penetrating the second stack, and a fourth bonding pad bonded with the second bonding pad. Drawings Fig. 1 is a diagram schematically illustrating an electronic system including a semiconductor device according to an example embodiment of the inventive concepts. Fig. 2A is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 2B is a cross-sectional view taken along line A-A' of fig. 2A to illustrate a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 3A is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 3B is a cross-sectional view taken along line B-B' of fig. 3A to illustrate a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 4 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 5 is an