CN-122028438-A - High bandwidth memory stack with side edge interconnect and liquid cooling structure

Abstract

A semiconductor package structure includes a memory stack, a substrate, a processor chip, and a liquid cooling structure. The memory stack includes a plurality of semiconductor wafers horizontally separated from one another, wherein each semiconductor wafer has a top surface, a bottom surface, and four sidewalls, wherein a second sidewall is opposite the first sidewall. The plurality of edge pads are disposed on the first sidewall of each semiconductor chip. The substrate is under the memory stack and electrically connected to the plurality of edge pads of each of the semiconductor chips. The processor die is over the substrate and adjacent to the memory stack. The liquid cooling structure is over the memory stack and the processor wafer and is thermally coupled to the memory stack and the processor wafer via the second sidewall of each of the semiconductor wafers and the top surface of the processor wafer.

Inventors

• TANG HEMING
• LU CHAOQUN

Assignees

• 铨心半导体异质整合股份有限公司
• 钰创科技股份有限公司

Dates

Publication Date

20260512

Application Date

20251111

Priority Date

20241112

Claims (20)

1. 1. A semiconductor package structure, comprising: A memory stack, comprising: a plurality of semiconductor chips horizontally separated from each other, wherein each semiconductor chip comprises a top surface, a bottom surface opposite to the top surface, and four side walls having a first side wall, a second side wall, a third side wall and a fourth side wall, wherein the second side wall is opposite to the first side wall, and a plurality of edge pads are arranged on the first side wall of each semiconductor chip, wherein the area of the bottom surface or the top surface is larger than that of any one of the four side walls, and A substrate under the memory stack and electrically connected to the plurality of edge pads of each of the semiconductor chips; A processor chip above the substrate and adjacent to the memory stack, including a top surface facing away from the substrate, and A liquid cooling structure is over the memory stack and the processor wafer and is thermally coupled to the memory stack and the processor wafer via the second sidewall of each of the semiconductor wafers and the top surface of the processor wafer.
2. 2. The semiconductor package structure of claim 1, further comprising: a first heat spreader over the processor die, wherein a first surface of the first heat spreader facing the processor die is substantially flush with the top surface of the processor die.
3. 3. The semiconductor package according to claim 2, wherein the liquid cooling structure comprises: A cover over the first heat sink, wherein the first heat sink further comprises a second surface facing the cover, wherein the second surface has a surface area greater than a surface area of the first surface, wherein the cover and the first heat sink together define a first chamber that allows a liquid coolant to flow therethrough.
4. 4. The semiconductor package according to claim 3, wherein the liquid cooling structure further comprises: A second heat sink comprising a third surface facing the second side walls of each of the semiconductor wafers, and a fourth surface opposite the third surface, the fourth surface having a surface area greater than the surface area of the third surface, wherein the second heat sink is configured to prevent the liquid coolant from contacting the second side walls of each of the semiconductor wafers, and wherein the cover and the second heat sink together define a second chamber allowing the liquid coolant to flow therethrough.
5. 5. The semiconductor package according to claim 4, wherein the memory stack further comprises an adhesive layer between the top surface of one semiconductor die and the bottom surface of an adjacent semiconductor die.
6. 6. The semiconductor package according to claim 3, wherein the second surface of the first heat spreader comprises a plurality of grooves extending in the direction of the flow of the liquid coolant.
7. 7. The semiconductor package according to claim 3, wherein the liquid cooling structure comprises: A cover over the second sidewalls of each of the semiconductor wafers of the memory stack, wherein the cover and the memory stack together define a third chamber that allows the liquid coolant to flow therethrough and contact the second sidewalls of the semiconductor wafers.
8. 8. The semiconductor package according to claim 1, wherein the liquid cooling structure further comprises an inflow port and an outflow port.
9. 9. The semiconductor package according to claim 7, further comprising a bonding layer over the top surface of the processor die and configured to bond the processor die to the first surface of the first heat spreader.
10. 10. The semiconductor package structure of claim 1, wherein the memory stack further comprises: An upwardly extending high thermal conductivity layer between two adjacent semiconductor wafers, wherein the upwardly extending high thermal conductivity layer has a thermal conductivity greater than SiO 2 .
11. 11. A semiconductor package structure, comprising: A memory stack, comprising: A plurality of semiconductor chips horizontally separated from each other, wherein each semiconductor chip comprises a top surface, a bottom surface opposite to the top surface, and four side walls having a first side wall, a second side wall, a third side wall and a fourth side wall, wherein the second side wall is opposite to the first side wall, and a plurality of edge pads are arranged on the first side wall of each semiconductor chip, wherein the area of the bottom surface or the top surface is larger than that of any one of the four side walls, and A substrate under the memory stack and electrically connected to the plurality of edge pads on the first sidewall of each of the semiconductor die; A processor wafer on the substrate including a top surface and a bottom surface opposite the top surface and adjacent to the memory stack, wherein the processor wafer and the memory stack define a height difference between the top surface of the processor wafer and the second sidewall of each of the semiconductor wafers, and A liquid cooling structure over the memory stack and the processor die.
12. 12. The semiconductor package structure of claim 11, further comprising: A first heat sink over the processor die, wherein a first surface of the first heat sink facing the processor die is substantially coplanar with the top surface of the processor die.
13. 13. The semiconductor package according to claim 12, wherein the liquid cooling structure comprises: A cover over the first heat sink, wherein the first heat sink further comprises a second surface facing the cover, the second surface having a surface area greater than a surface area of the first surface, wherein the cover and the first heat sink together define a chamber that allows a liquid coolant to flow therethrough.
14. 14. The semiconductor package according to claim 13, wherein the liquid cooling structure further comprises: A second heat sink comprising a third surface facing the second side walls of each of the semiconductor chips and a fourth surface opposite the third surface, the fourth surface having a surface area greater than the surface area of the third surface, wherein the second heat sink is configured to avoid a liquid coolant contacting the second side walls of each of the semiconductor chips.
15. 15. The semiconductor package according to claim 12, wherein the liquid cooling structure comprises: A cover over the first heat spreader and the second sidewalls of each of the semiconductor die, wherein the cover, the first heat spreader and the memory stack together define a chamber that allows a liquid coolant to flow therethrough.
16. 16. The semiconductor package structure of claim 11, further comprising: A memory controller die over the substrate and under the memory stack, wherein the memory controller die is electrically connected to the plurality of edge pads of each of the semiconductor dies.
17. 17. The semiconductor package structure of claim 11, further comprising: A memory controller die within the memory stack and over the substrate, wherein the memory controller die is electrically connected to the plurality of edge pads of each of the semiconductor dies.
18. 18. The semiconductor package according to claim 11, wherein the substrate comprises: A laminated substrate under the memory stack and the processor die, and An interposer between the laminate substrate and the memory stack and the processor die, wherein the interposer includes a plurality of vias through a thickness of the interposer.
19. 19. The semiconductor package structure of claim 11, further comprising: a redistribution layer under the memory stack and electrically connected to the plurality of edge pads of each of the semiconductor die.
20. 20. The semiconductor package according to claim 11, wherein the substrate comprises an embedded interconnect die that is part of the plurality of edge pads that electrically connect the processor die to at least one of the semiconductor die of the memory stack.

Description

High bandwidth memory stack with side edge interconnect and liquid cooling structure Cross reference to related applications The present application claims from U.S. provisional application Ser. No. 63/719,398, U.S. provisional application Ser. No. 63/730,470, and U.S. provisional application Ser. No. 18/471,670 filed on 21, 2023, and 2022, which claims priority from U.S. provisional application Ser. No. 63/409,852 filed on 26, 2022, 9, are incorporated herein by reference in their entirety. Technical Field The present disclosure relates to semiconductor packages including memory stacks and liquid cooling structures for the memory stacks, and more particularly to liquid cooling structures having side edge interconnects and high bandwidth memory stacks and the high bandwidth memory stacks. Background As artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) and machine learning (MACHINE LEARNING, ML) continue to change the various industries, AI wafers (especially general purpose GPUs for data centers) will achieve a significant growth of 2.6 times in 2024 to 2030, but also drive a significant shift in the packaging required to protect and connect these devices. Taking the most advanced GB200 GPU of NVIDIA as an example, the power consumption per chip is up to 1200W, and may soon be higher. GB200 GPU is packaged with extremely thin 2.5D ICs, with its high bandwidth memory stack (high-bandwidth memory stacks, HBMs) placed laterally (side-by-side) with the GPU on an interposer, and with the combination of thermal interface materials (THERMAL INTERFACE MATERIALS, TIMs), heat sinks, and cold plates attached to the back sides of the GPU and HBMs for direct liquid cooling of the wafer. Direct-to-chip liquid cooling (Direct-to-chip liquid cooling) is a thermal management technique in which the coolant is delivered directly to a cold plate in Direct contact with the processor or wafer package. Fig. 1 shows a 2.5D IC structure 10 comprising a HBM structure 11 composed of a plurality of DRAM memory dies 111 and a controller 112 having through-silicon vias (TSVs), a logic die 12 (e.g., GPU or SoC die), a silicon interposer 13 having TSVs, and a package substrate 14, wherein the HBM structure 11 and the logic die 12 are stacked on the silicon interposer 13, and the silicon interposer 13 is stacked on the package substrate 14. Although the power involved by the HBM is much less than the GPU, as the HBM expands from HBM2E (19W) to HBM4 (48/80W) or beyond, it is also expected that more heat will need to be dissipated as the number of wafers in the HBM stack increases from 5 (HBM 2E) to 17 (HBM 4) or beyond. High power and high energy processors, particularly GPUs, generate large amounts of heat, which presents serious challenges to data center operators. While efficient thermal management is required to ensure that the wafers in the HBM, and particularly the bottom and middle wafers in the HBM, maintain their optimal operating temperatures. Based on the complexity and demand of AI workloads, and the expected increase in GPU and HBM power, conventional cold plate cooling quickly loses competitiveness-efficient thermal management is not just an option but is necessary to ensure optimal performance and operational stability. Poor thermal management can lead to hardware degradation, downtime, performance bottlenecks, and higher operating costs. In addition to thermal challenges, HBMs are expected to be increasingly faced with other problems including (a) excessive costs due to difficulty in achieving high DRAM yields and lack of known good die (involving larger numbers of cost-effective Through Silicon Vias (TSVs)), (b) limited numbers of HBM suppliers, (c) lack of priority and support for HBM customization and optimization by these suppliers, (d) migration from copper pillar microbumping and Molded Underfill (MUF) based flip-chip processes to very cost-effective copper hybrid bonding processes (which are still in the start-up phase in the future HBMs), and (e) high-end advanced packaging capability and/or throughput are typically bottlenecks of existing three-large suppliers, which together affect HBM stable supply. Disclosure of Invention According to a first aspect of the present disclosure, a semiconductor package includes a memory stack, a substrate, a processor die, and a liquid cooling structure. The memory stack includes a plurality of semiconductor dies horizontally spaced apart from each other, wherein each semiconductor die includes a top surface, a bottom surface opposite the top surface, and four sidewalls having a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, wherein the second sidewall is opposite the first sidewall, and a plurality of edge pads are disposed on the first sidewall of each semiconductor die, wherein an area of the bottom surface or the top surface is greater than an area of any of the four sidewalls. The substrate is located under the memory stack and is electrically c