CN-122028439-A - Memory chip, logic chip, chip stacking structure and memory

Abstract

The invention belongs to the technical field of semiconductors, and provides a memory chip, a logic chip, a chip stacking structure and a memory, which aim at the problem that signal connection between a memory chip and a logic chip in a three-dimensional chip stacking structure is complex, wherein the memory chip comprises 2A channel signal areas which are sequentially arranged along a first direction, each channel signal area comprises a first data signal area and a second data signal area which are arranged along the first direction, the first data signal area in the ith channel signal area and the first data signal area in the (2A-i+1) th channel signal area are symmetrical about a second axis, and the second data signal area in the ith channel signal area and the second data signal area in the (2A-i+1) th channel signal area are symmetrical about the second axis. Therefore, after the three-dimensional chip stacking structure is formed, the positions of the first data signal area and the second data signal area of the memory chip and the logic chip are aligned along the third direction, so that the complexity of signal routing is reduced.

Inventors

• ZHANG JIARUI

Assignees

• 极芯拓方技术(上海)有限公司

Dates

Publication Date

20260512

Application Date

20260408

Claims (20)

1. 1. A memory chip, wherein an active surface of the memory chip has a first axis and a second axis, the first axis and the second axis perpendicularly intersecting a midpoint of the active surface; the memory chip comprises 2A channels which are sequentially arranged along a first direction, wherein each channel comprises 1 channel signal area, and 2A channel signal areas are sequentially arranged along the first direction; Each of the channel signal regions includes 2n sets of conductive vias, and 2n sets of conductive vias in each of the channel signal regions are symmetrical about the first axis; all conductive path groups of 2A channel signal regions in the memory chip are integrally symmetrical about the second axis; Each channel comprises a first pseudo channel and a second pseudo channel, each channel signal region comprises a first data signal region and a second data signal region which are arranged along a first direction, a conductive path group in the first data signal region is used for transmitting a data signal of the corresponding first pseudo channel, and a conductive path group in the second data signal region is used for transmitting a data signal of the corresponding second pseudo channel; The first data signal area in the ith channel signal area and the first data signal area in the (2A-i+1) th channel signal area are symmetrical about the second axis, the second data signal area in the ith channel signal area and the second data signal area in the (2A-i+1) th channel signal area are symmetrical about the second axis, A is more than or equal to i and more than or equal to 1, and i, n and A are all positive integers.
2. 2. The memory chip of claim 1, wherein each of the channel signal regions further comprises a control signal region; In the same channel signal region, the control signal region is arranged between the first data signal region and the second data signal region along the first direction; the conductive path group in the control signal area is used for transmitting control signals of the corresponding first pseudo channel and the corresponding second pseudo channel.
3. 3. The memory chip of claim 1, wherein each channel signal region further comprises a fifth axis, the fifth axis and the first axis perpendicularly intersecting a center of the channel signal region, and wherein 2n of the conductive via groups in a same channel signal region are symmetrical about the fifth axis and about the first axis.
4. 4. The memory chip of claim 1, wherein each of the conductive via groups has a third axis and a fourth axis, the third axis and the fourth axis being perpendicular to each other and intersecting a center of the conductive via group, the third axis being parallel to the first axis, each of the conductive via groups comprising 4 conductive vias distributed in a 2 x 2 array, the 4 conductive vias being symmetrical about the third axis and symmetrical about the fourth axis, the conductive vias extending through a substrate of the memory chip in a third direction, the third direction being perpendicular to the active face.
5. 5. The memory chip of claim 4 wherein each of said conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via, said first conductive via and said second conductive via being symmetrical about said third axis, said third conductive via and said fourth conductive via being symmetrical about said fourth axis in each of said conductive via groups.
6. 6. The memory chip of claim 5, wherein the active surface is divided into a first region, a second region, a third region, and a fourth region by the first axis and the second axis; (1) The first conductive via in the first region is symmetrical with the second conductive via in the second region about the first axis, and the first conductive via in the first region is also symmetrical with the fourth conductive via in the fourth region about the second axis; the third conductive via in the third region is symmetrical with the fourth conductive via in the fourth region about the first axis, and the third conductive via in the third region is also symmetrical with the second conductive via in the second region about the second axis; (2) The second conductive via in the first region is symmetrical with the first conductive via in the second region about the first axis, and the second conductive via in the first region is also symmetrical with the third conductive via in the fourth region about the second axis; The fourth conductive via in the third region is symmetrical with the third conductive via in the fourth region about the first axis, and the fourth conductive via in the third region is also symmetrical with the first conductive via in the second region about the second axis; (3) The third conductive via in the first region is symmetrical with the fourth conductive via in the second region about the first axis, and the third conductive via in the first region is also symmetrical with the second conductive via in the fourth region about the second axis; The first conductive via in the third region is symmetrical with the second conductive via in the fourth region about the first axis, and the first conductive via in the third region is also symmetrical with the fourth conductive via in the fourth region about the second axis; (4) The fourth conductive via in the first region is symmetrical with the third conductive via in the second region about the first axis, and the fourth conductive via in the first region is also symmetrical with the first conductive via in the fourth region about the second axis; The second conductive via in the third region is symmetrical with the first conductive via in the fourth region about the first axis, and the second conductive via in the third region is also symmetrical with the third conductive via in the second region about the second axis.
7. 7. The memory chip of claim 5, wherein each of said channels further comprises 2n first transceivers, each of said first transceivers being coupled to a corresponding one of said first conductive paths within said channel; The first transceiver is used for receiving signals transmitted by the correspondingly coupled first conductive paths or generating signals transmitted outwards through the correspondingly coupled first conductive paths.
8. 8. The memory chip of claim 6, wherein the memory chip further comprises a memory chip, Each set of conductive vias is used to transmit 2 different types of signals, 2 of the conductive vias symmetrical about the first axis are used to transmit the same type of signals for the same channel signal region, and 2 of the conductive vias symmetrical about the second axis are used to transmit the same type of signals for different channel signal regions.
9. 9. The memory chip according to any one of claims 1 to 8, wherein, The conductive paths comprise conductive through holes, the conductive through holes are prepared through any one process or a plurality of processes of a first through hole process via-first, a middle through hole process via-middle, a rear through hole process via-last and a rear through hole process backsidevia-last, and different conductive paths in the same memory chip are electrically isolated.
10. 10. A logic chip is characterized in that an active surface of the logic chip is provided with a first axis and a second axis, and the first axis and the second axis are perpendicularly intersected at the midpoint of the active surface; Each of the channel signal regions includes 2n sets of conductive vias, and 2n sets of conductive vias in each of the channel signal regions are symmetrical about the first axis; all conductive path groups of 2A channel signal regions in the logic chip are integrally symmetrical about the second axis; The logic chip comprises 2A channel signal areas and 2A channels, wherein the 2A channel signal areas of the logic chip are in one-to-one correspondence with the 2A channels of the memory chip, each channel signal area is divided into a first data signal area and a second data signal area which are arranged along a first direction, a conductive path group in the first data signal area is used for transmitting data signals of a first pseudo channel in the corresponding channel, and a conductive path group in the second data signal area is used for transmitting data signals of a second pseudo channel in the corresponding channel; The first data signal area in the ith channel signal area and the first data signal area in the (2A-i+1) th channel signal area are symmetrical about the second axis, the second data signal area in the ith channel signal area and the second data signal area in the (2A-i+1) th channel signal area are symmetrical about the second axis, A is more than or equal to i and more than or equal to 1, and i, n and A are all positive integers.
11. 11. The logic chip of claim 10, wherein each of the channel signal regions further comprises a control signal region; For the same channel signal region, the control signal region is disposed between the first data signal region and the second data signal region along the first direction; the conductive path group in the control signal area is used for transmitting control signals of the corresponding first pseudo channel and the corresponding second pseudo channel.
12. 12. The logic chip of claim 11 wherein each of the channel signal regions further comprises a fifth axis, the fifth axis and the first axis perpendicularly intersecting a center of the channel signal region, and wherein 2n sets of the conductive vias in the same channel signal region are symmetrical about the fifth axis and about the first axis.
13. 13. The logic chip of claim 12 wherein each of the conductive via groups has a third axis and a fourth axis, the third axis and the fourth axis being perpendicular to each other and intersecting a center of the conductive via group, the third axis being parallel to the first axis, each of the conductive via groups comprising 4 conductive vias distributed in a 2 x2 array, the 4 conductive vias being symmetrical about the third axis and symmetrical about the fourth axis, the conductive vias extending in a third direction, the third direction being perpendicular to the active face.
14. 14. The logic chip of claim 13 wherein each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via, the first conductive via and the second conductive via being symmetrical about the third axis, the third conductive via and the fourth conductive via being symmetrical about the third axis in each of the conductive via groups.
15. 15. The logic chip of claim 14, wherein the active surface is divided by the first axis and the second axis into a first region, a second region, a third region, and a fourth region; (1) The first conductive via in the first region is symmetrical with the second conductive via in the second region about the first axis, and the first conductive via in the first region is also symmetrical with the fourth conductive via in the fourth region about the second axis; the third conductive via in the third region is symmetrical with the fourth conductive via in the fourth region about the first axis, and the third conductive via in the third region is also symmetrical with the second conductive via in the second region about the second axis; (2) The second conductive via in the first region is symmetrical with the first conductive via in the second region about the first axis, and the second conductive via in the first region is also symmetrical with the third conductive via in the fourth region about the second axis; The fourth conductive via in the third region is symmetrical with the third conductive via in the fourth region about the first axis, and the fourth conductive via in the third region is also symmetrical with the first conductive via in the second region about the second axis; (3) The third conductive via in the first region is symmetrical with the fourth conductive via in the second region about the first axis, and the third conductive via in the first region is also symmetrical with the second conductive via in the fourth region about the second axis; The first conductive via in the third region is symmetrical with the second conductive via in the fourth region about the first axis, and the first conductive via in the third region is also symmetrical with the fourth conductive via in the fourth region about the second axis; (4) The fourth conductive via in the first region is symmetrical with the third conductive via in the second region about the first axis, and the fourth conductive via in the first region is also symmetrical with the first conductive via in the fourth region about the second axis; The second conductive via in the third region is symmetrical with the first conductive via in the fourth region about the first axis, and the second conductive via in the third region is also symmetrical with the third conductive via in the second region about the second axis.
16. 16. The logic chip of claim 14, wherein each of said lanes further comprises (2nx4) second transceivers, each of said second transceivers being coupled in a one-to-one correspondence with one of said conductive vias within a corresponding one of said lanes; the second transceiver is used for receiving signals transmitted by the conductive paths of the corresponding connection or generating signals transmitted outwards through the conductive paths of the corresponding connection.
17. 17. The logic chip of claim 14 wherein each set of conductive vias is configured to transmit 2 different types of signals, 2 of the conductive vias symmetrical about the first axis are configured to transmit the same type of signal for the same channel signal region, and 2 of the conductive vias symmetrical about the second axis are configured to transmit the same type of signal for different channel signal regions.
18. 18. The logic chip according to any one of claims 10 to 17, wherein, The conductive paths comprise silicon through holes, the silicon through holes are prepared through any one process or a plurality of processes of a first through hole process via-first, a middle through hole process via-middle, a later through hole process via-last and a back through hole process backsidevia-last, and different conductive paths in the same memory chip are electrically isolated.
19. 19. A chip stack structure comprising the logic chip according to any one of claims 10 to 18 and at least one stack unit, the logic chip and at least one stack unit being stacked in sequence along a third direction, each stack unit comprising a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along the third direction, the third direction being perpendicular to an active surface of each of the memory chips, the first memory chip, the second memory chip, the third memory chip and the fourth memory chip being the memory chip according to any one of claims 1 to 9; the logic chip and the first memory chip are stacked in a face-to-back or back-to-back manner; The first memory chip and the second memory chip are stacked in a face-to-face manner; the second memory chip and the third memory chip are stacked in a back-to-back manner; the third memory chip and the fourth memory chip are stacked in a face-to-face manner; The projection of the 2A first data signal areas of the logic chip and the projection of the 2A second data signal areas of the memory chip along the third direction are overlapped in a one-to-one correspondence manner.
20. 20. The chip stacking structure as recited in claim 19, wherein, The ith channel signal area in the first memory chip, the (2A+1) th channel signal area in the second memory chip, the (2A+1-i) th channel signal area in the third memory chip and the ith channel signal area in the fourth memory chip are aligned along a third direction.

Description

Memory chip, logic chip, chip stacking structure and memory Technical Field The present disclosure relates to semiconductor technology, and more particularly, to a memory chip, a logic chip, a chip stack structure, and a memory. Background With the development of integrated circuit technology, the production process of semiconductor devices has advanced significantly. In recent years, however, the development of two-dimensional semiconductor technology has encountered various challenges, physical limitations, existing development technology limitations, storage electron density limitations, and the like. In this context, to address the difficulties encountered with two-dimensional semiconductor devices and to pursue lower production costs per memory cell, multiple chips may be stacked using bonding processes (e.g., hybrid bonding, bump bonding Bumping, wire bonding) to form a three-dimensional semiconductor device. However, for the three-dimensional semiconductor device, the connection structure between different chips still has the problems of large parasitic capacitance, large parasitic resistance and the like, and the signal transmission quality is affected. Disclosure of Invention The embodiment of the disclosure provides a memory chip, a logic chip, a chip stacking structure and a memory. The technical scheme of the embodiment of the disclosure is realized as follows: In a first aspect, embodiments of the present disclosure provide a memory chip, an active surface of the memory chip having a first axis and a second axis, the first axis and the second axis perpendicularly intersecting a midpoint of the active surface, the memory chip including 2A channels arranged in sequence along a first direction, each channel including 1 channel signal region, the 2A channel signal regions arranged in sequence along the first direction; Each of the channel signal regions includes 2n sets of conductive vias, and 2n sets of conductive vias in each of the channel signal regions are symmetrical about the first axis; all conductive path groups of 2A channel signal regions in the memory chip are integrally symmetrical about the second axis; Each channel comprises a first pseudo channel and a second pseudo channel, each channel signal region comprises a first data signal region and a second data signal region which are arranged along a first direction, a conductive path group in the first data signal region is used for transmitting a data signal of the corresponding first pseudo channel, and a conductive path group in the second data signal region is used for transmitting a data signal of the corresponding second pseudo channel; The first data signal area in the ith channel signal area and the first data signal area in the (2A-i+1) th channel signal area are symmetrical about the second axis, the second data signal area in the ith channel signal area and the second data signal area in the (2A-i+1) th channel signal area are symmetrical about the second axis, A is more than or equal to i and more than or equal to 1, and i, n and A are all positive integers. In some embodiments, each channel signal region further comprises a control signal region, wherein the control signal region is arranged between the first data signal region and the second data signal region along the first direction in the same channel signal region, and the conductive path group in the control signal region is used for transmitting control signals of the corresponding first pseudo channel and the corresponding second pseudo channel. In some embodiments, each of the channel signal regions further comprises a fifth axis, the fifth axis and the first axis perpendicularly intersecting the center of the channel signal region, and 2n of the conductive via groups in the same channel signal region are symmetrical about the fifth axis and about the first axis. In some embodiments, each of the conductive via groups has a third axis and a fourth axis, the third axis and the fourth axis being perpendicular to each other and intersecting a center of the conductive via group, the third axis being parallel to the first axis, each of the conductive via groups comprising 4 conductive vias distributed in a 2 x 2 array, the 4 conductive vias being symmetrical about the third axis and symmetrical about the fourth axis, the conductive vias extending through the substrate of the memory chip in a third direction, the third direction being perpendicular to the active face. In some embodiments, each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via, the first conductive via and the second conductive via being symmetrical about the third axis, the third conductive via and the fourth conductive via being symmetrical about the third axis, the first conductive via and the fourth conductive via being symmetrical about the fourth axis in each of the conductive via groups. In some embodiments, th