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CN-122028441-A - On-chip capacitor structure and preparation method thereof

CN122028441ACN 122028441 ACN122028441 ACN 122028441ACN-122028441-A

Abstract

The application discloses an on-chip capacitor structure and a preparation method thereof, wherein the structure comprises a substrate, a first metal layer and a second metal layer, wherein the first metal layer is positioned at the center of the first surface of the substrate; the second metal layer is divided into a first area and a second area, the first area is located on the first surface of the substrate, the second area is located above the first metal layer, the second area is higher than the first area, an upper-lower distance is arranged between the first metal layer and the second metal layer, a relative area is arranged at an overlapped part between the second metal layer and the first metal layer of the second area, and the upper-lower distance and the relative area are used for regulating capacitance.

Inventors

  • YANG CHUHONG
  • SU TANG
  • YU HAIFENG

Assignees

  • 北京量子信息科学研究院

Dates

Publication Date
20260512
Application Date
20251229

Claims (10)

  1. 1. An on-chip capacitor structure, comprising: The substrate is provided with a plurality of holes, A first metal layer located in a central region of the first surface of the substrate; A second metal layer divided into a first region and a second region, wherein the first region is positioned on the first surface of the substrate, and the second region is positioned above the first metal layer; The second area is higher than the first area, so that an upper-lower distance is reserved between the first metal layer and the second metal layer; A portion of the second region where the second metal layer overlaps the first metal layer has an opposite area; the upper and lower pitches and the relative areas are used for regulating and controlling capacitance.
  2. 2. The capacitor-on-chip structure of claim 1, wherein the first metal layer and the second metal layer have a cavity or a silicon oxide layer therebetween.
  3. 3. The capacitor-on-chip structure of claim 1 or 2, wherein the substrate thickness is 300-500nm; the thickness of the first metal layer is 100-400nm; the thickness of the second metal layer is 400-600nm.
  4. 4. The capacitor on chip structure of claim 2, wherein the silicon oxide layer has a thickness of 200-3000nm.
  5. 5. The capacitor-on-chip structure of claim 1, wherein the pitch is 200-3000nm.
  6. 6. The capacitor-on-chip structure of claim 1 or 5, wherein the relative area is 2500-250000 μm 2 .
  7. 7. The capacitor-on-chip structure of claim 6, wherein the substrate is a sapphire substrate or a silicon substrate; The first metal layer is made of aluminum, tantalum or niobium; The second metal layer is made of aluminum.
  8. 8. A method of making the capacitor-on-chip structure of any one of claims 1-7, comprising: Depositing a first metal film on a first surface of a substrate; spin-coating a first photoresist on the surface of the first metal film to prepare a first photoresist pattern; Etching the first photoresist pattern to obtain a first metal layer, and preparing a bottom circuit; spin-coating a second photoresist on the surface of the bottom circuit to prepare a second photoresist pattern; performing thermal reflux treatment on the second photoresist pattern to obtain a second photoresist pattern with an arc-shaped edge; Depositing a second metal film on the first surface of the substrate and the surface of the second photoresist pattern with the arc-shaped edge; spin-coating a third photoresist on the surface of the second metal film to prepare a third photoresist pattern; And etching the third photoresist pattern, and removing the residual first photoresist, second photoresist and third photoresist to obtain a second metal layer, thus obtaining the on-chip capacitor structure.
  9. 9. The method of manufacturing a chip capacitor structure according to claim 8, wherein the thermal reflow process includes placing the substrate on a hot plate, heating from 110-120 ℃ to a target 140-160 ℃ for 6-10 minutes, and turning the edge of the second photoresist pattern into an arc shape.
  10. 10. A method of making the capacitor-on-chip structure of any one of claims 1-7, comprising: Depositing a first metal film on a first surface of a substrate; spin-coating a first photoresist on the surface of the first metal film to prepare a first photoresist pattern; Etching the first photoresist pattern to obtain a first metal layer, and preparing a bottom circuit; spin-coating a second photoresist and a third photoresist on the surface of the bottom circuit to prepare a second photoresist pattern; Depositing silicon oxide on the surface of the first metal layer through the second photoresist pattern, and stripping the second photoresist and the third photoresist to obtain a silicon oxide layer covering the surface of the first metal layer; Depositing a second metal film on the first surface of the substrate and the surface of the silicon oxide layer; spin-coating a fourth photoresist on the surface of the second metal film to prepare a third photoresist pattern; And etching the third photoresist pattern, and removing the residual fourth photoresist to obtain a second metal layer, thus obtaining the on-chip capacitor structure.

Description

On-chip capacitor structure and preparation method thereof Technical Field The application relates to the technical field of superconducting quantum chips, in particular to an on-chip capacitor structure and a preparation method thereof. Background The on-chip capacitor of the superconducting quantum chip is a core passive element, and the performance (such as low loss and high stability) directly determines the coherence time and the calculation reliability of the quantum bit. In order to improve the chip integration and performance, current research is advancing from traditional planar design to a more compact and efficient structure. At present, capacitive devices on superconducting quantum chips are two-dimensional capacitors, such as coupling capacitors and bit capacitors, are realized by metal films which are close to each other, and electric fields are distributed between the metal films. The capacitance is approximately proportional to the length of the opposite edges of the two metal films. In some cases, if a larger capacitance is required, a longer metal film opposite edge needs to be designed, which may occupy more chip area, resulting in lower integration. Disclosure of Invention In order to solve the above-mentioned shortcomings in the art, the present application is directed to an on-chip capacitor structure and a method for manufacturing the same. According to an aspect of the present application, there is provided an on-chip capacitor structure comprising: The substrate is provided with a plurality of holes, A first metal layer located in a central region of the first surface of the substrate; The second metal layer is divided into a first area and a second area, the first area is positioned on the first surface of the substrate, and the second area is positioned above the first metal layer; The second area is higher than the first area, so that an upper-lower distance is reserved between the first metal layer and the second metal layer; the overlapped part between the second metal layer and the first metal layer of the second area has a relative area; The up-down spacing and the relative area are used for regulating and controlling the capacitance. According to some embodiments of the application, there is a cavity or a silicon oxide layer between the first metal layer and the second metal layer. According to some embodiments of the application, the substrate has a thickness of 300-500nm, the first metal layer has a thickness of 100-400nm, and the second metal layer has a thickness of 400-600nm. According to some embodiments of the application, the silicon oxide layer has a thickness of 200-3000nm. According to some embodiments of the application, the pitch is 200-3000nm. According to some embodiments of the application, the relative area is 2500-250000 μm 2. According to some embodiments of the application, the substrate is a sapphire substrate or a silicon substrate, the material of the first metal layer is aluminum, tantalum or niobium, and the material of the second metal layer is aluminum. According to another aspect of the present application, there is also provided a method for manufacturing the above-mentioned on-chip capacitor structure, including: Depositing a first metal film on a first surface of a substrate; spin-coating a first photoresist on the surface of the first metal film to prepare a first photoresist pattern; etching the first photoresist pattern to obtain a first metal layer, and preparing a bottom circuit; Spin-coating a second photoresist on the surface of the bottom circuit to prepare a second photoresist pattern; performing thermal reflux treatment on the second photoresist pattern to obtain a second photoresist pattern with an arc-shaped edge; Depositing a second metal film on the first surface of the substrate and the surface of the second photoresist pattern with the edge being arc-shaped; spin-coating a third photoresist on the surface of the second metal film to prepare a third photoresist pattern; and etching the third photoresist pattern, and removing the residual first photoresist, second photoresist and third photoresist to obtain a second metal layer, thus obtaining the on-chip capacitor structure. According to some embodiments of the present application, the thermal reflow process includes placing the substrate on a hot plate, heating from 110-120 ℃ to 140-160 ℃ of the target, for a period of 6-10 minutes, and causing the edges of the second photoresist pattern to become curved. According to an aspect of the present application, there is provided another method for manufacturing the above-mentioned on-chip capacitor structure, including: Depositing a first metal film on a first surface of a substrate; spin-coating a first photoresist on the surface of the first metal film to prepare a first photoresist pattern; etching the first photoresist pattern to obtain a first metal layer, and preparing a bottom circuit; spin-coating a second photoresist and a th