CN-122028446-A - IGBT device with low switching loss and preparation method thereof

CN122028446ACN 122028446 ACN122028446 ACN 122028446ACN-122028446-A

Abstract

The invention relates to a power semiconductor technology, in particular to a low-switching-loss IGBT device and a preparation method thereof, wherein a gate oxide layer is arranged on the inner walls of a first groove and a second groove, the lower part of the low-switching-loss IGBT device is filled with a virtual groove gate, and the upper part of the low-switching-loss IGBT device is filled with an effective groove gate, so that a split groove gate structure is formed, the Miller capacitance effect in the switching process of the device is effectively reduced, the coupling effect of voltage change to grid potential in the switching-on stage is weakened, the overlapping time of voltage and current in the switching-on process is further shortened, and the switching-on loss of the device is obviously reduced; by arranging the deep P region, the transport path of the carriers in the device is reasonably guided and strengthened, the extraction rate of the carriers in the drift region in the turn-off process is accelerated, the current tailing phenomenon in the turn-off stage is effectively restrained, the turn-off time is shortened, and the turn-off loss of the device is obviously reduced.

Inventors

Zheng Gege
LI ZEHONG
Jing Shuolei
JIN ZHAOQING
YANG LONG
CHEN YUYANG
ZHENG LIKUN

Assignees

电子科技大学

Dates

Publication Date: 20260512
Application Date: 20260313

Claims (8)

1. The utility model provides a low switching loss's IGBT device, includes heavily doped P district, field cut-off region, N type drift region that sets gradually from bottom to top, its characterized in that: The N-type drift region is divided into a first region and a second region adjacent to the first region, a carrier storage layer is formed on the first region of the N-type drift region, a deep P region is formed on the second region and extends downwards to the inside of the N-type drift region, the top of the carrier storage layer is flush with the top of the deep P region, a P-type body region is formed on the carrier storage layer, a P+ emitter region and a P+ contact region are formed on the P-type body region in the same layer, and the carrier storage layer, the deep P region, the P-type body region, the N+ emitter region and the P+ contact region jointly form a surface source layer region structure; an interlayer dielectric layer and a top metal electrode are sequentially formed on the surface source layer region structure, and a contact hole which longitudinally penetrates through the interlayer dielectric layer is formed on the interlayer dielectric layer; The surface source layer region structure is internally provided with two groove structures with the same structure size, namely a first groove and a second groove, the inner walls of the two groove structures are covered with a gate oxide layer, polysilicon materials are filled in the grooves, the polysilicon materials in each groove structure are divided into an upper part and a lower part by the gate oxide layer, wherein the upper part polysilicon forms an effective groove gate, the lower part polysilicon forms a virtual groove gate, electric isolation is realized between the effective groove gate and the virtual groove gate through the gate oxide layer, the first groove is positioned at one side of an N+ emitter region and is clung to the N+ emitter region, the top end of the first groove is flush with the top of the N+ emitter region, the bottom end of the first groove sequentially penetrates through a P-type body region and a carrier storage layer and extends into the N-type drift region, the second groove and the first groove are arranged at intervals transversely, the middle of a P+ contact region is arranged between the first groove and the second groove, the top end of the first groove is flush with the P+ contact region, the bottom end of the first groove penetrates through the P-type body region and the deep P region in sequence and extends into the N-type drift region.
2. The low switching loss IGBT device of claim 1 wherein the thickness is defined as the longitudinal direction and the dummy trench gate is the same as the thickness of the active trench gate.
3. The IGBT device of claim 1, wherein the N drift region has a thickness of 100 μm.
4. The IGBT device of claim 3, wherein the effective trench gate has a thickness greater than a thickness of the P-type body region, and the dummy trench gate has a thickness less than a thickness of the deep P-type body region and greater than a thickness of the carrier storage layer.
5. The low switching loss IGBT device of claim 1 wherein said active trench gate is electrically connected to a gate potential and said dummy trench gate is electrically connected to an emitter potential.
6. The preparation method of the IGBT device with low switching loss is used for manufacturing the IGBT device with low switching loss, and is characterized by comprising the following steps of: S1, providing an N-type monocrystalline silicon substrate to form an N drift region; s2, injecting N-type impurities into the upper surface of the N drift region and pushing a well to form a carrier storage layer; S3, injecting P-type impurities into the carrier storage layer at the position corresponding to the second region of the N drift region and pushing the P-type impurities into the carrier storage layer to form a deep P region; s4, etching to form a second groove penetrating through the deep P region and a first groove penetrating through the carrier storage layer, and thermally growing a gate oxide layer on the inner surfaces of the first groove and the second groove to form a gate oxide region; S5, respectively depositing a first polysilicon layer at the lower parts of the first groove and the second groove, and etching to form a virtual groove gate; s6, forming insulation isolation on the heat-generated oxide layer on the upper surface of the virtual trench gate, and then depositing and etching a second polysilicon layer on the upper parts of the first trench and the second trench to form an effective trench gate; s7, injecting P-type impurities into the carrier storage layer and the deep P region and pushing the P-type impurities to form a P-type body region; S8, injecting N-type impurities into the P-type body region and annealing to form an N+ emitter region, wherein the N+ emitter region is positioned between the first groove and the second groove and is tightly attached to the side wall of the first groove; s9, depositing a borophosphosilicate glass layer on the surface of the device obtained in the step S8, and etching to form an interlayer dielectric layer and expose contact holes of the N+ emitter region and the region of the P+ contact region; S10, injecting P-type impurities into the P-type body region through the contact hole and annealing to form a P+ contact region, wherein the P+ contact region is positioned at two sides of the second groove, clings to the side wall of the second groove and is flush with the top of the N+ emitter region; s11, depositing and patterning a metal layer on the interlayer dielectric layer to form a top metal electrode electrically connected with the N+ emitter region and the P+ contact region through the contact hole; And S12, thinning the back surface of the N-type drift region, implanting ions, annealing to form a field stop region, and then implanting boron ions, annealing to form a heavily doped P region.
7. The method of manufacturing a low switching loss IGBT device of claim 6 wherein in step S1 the N type single crystal silicon substrate has a crystal orientation of <100>.
8. The method of manufacturing a low switching loss IGBT device according to claim 6, wherein in step S3, the P-type impurity used to form the deep P region is boron ions.

Description

IGBT device with low switching loss and preparation method thereof Technical Field The invention relates to the technical field of power semiconductors, in particular to a low-switching-loss IGBT device and a preparation method thereof. Background IGBT (InsulatedGateBipolarTransistor ) devices are widely applied to power electronic systems such as new energy power generation, rail transit, electric transmission, industrial frequency conversion and the like because of the high input impedance characteristic of MOSFETs and the low conduction loss advantage of bipolar transistors. With the development of power electronic devices to high efficiency, high power density and high frequency, power loss in the device working process has become one of key factors limiting the improvement of the overall performance of the system, and especially the problem of dynamic loss of IGBTs in the switching process is increasingly prominent. In practical applications, the total loss of an IGBT is generally composed of both conduction loss and switching loss. In the existing design, the conduction voltage drop of the device is reduced to a certain extent by introducing a carrier storage layer and a micro-groove structure, but the proportion of the switching loss in the total loss continuously rises under the high-frequency or high-current working condition, and even becomes a dominant factor. On the one hand, during the turn-on process of the IGBT, the device is switched from a high resistance state to an on state, the collector-emitter voltage drops rapidly, and the current rises rapidly. In the process, the gate driving signal is required to charge and discharge parasitic capacitance in the device, especially parasitic capacitance (miller capacitance) between the gate and the collector, and obvious charge coupling effect can be generated in the voltage change stage, so that the gate voltage is limited to change in a certain interval, and a longer miller voltage platform is formed. During this plateau phase, the device voltage is at a higher level simultaneously with the current, thereby creating significant turn-on energy loss. With the improvement of the voltage withstand level of the device or the increase of the unit area, the Miller capacitance effect is further enhanced, so that the energy loss in the starting process is difficult to effectively reduce, and the performance of the IGBT in high-frequency and low-loss application scenes is limited. On the other hand, during turn-off of the IGBT, the device switches from an on state to an off state, the collector current decreases and the voltage increases. Since the IGBT has bipolar conductivity, a large number of carriers accumulate in the drift region in its on state, which need to be gradually disappeared by recombination or extraction when turned off. In this process, the device tends to exhibit a significant current tailing phenomenon, which not only prolongs the turn-off time, but also continues to turn on at higher voltages, thereby significantly increasing turn-off energy loss. Such turn-off loss not only affects the overall efficiency of the device, but may also lead to increased junction temperature and thermal stress of the device, thereby adversely affecting the reliability and lifetime of the device. Therefore, there is a need for an IGBT device structure and a method for manufacturing the same that can effectively increase the switching speed of the device and reduce the switching loss without increasing the on-voltage drop of the device. Disclosure of Invention In view of the above, the present application provides an IGBT device with low switching loss and a method for manufacturing the same, so as to increase the switching speed of the device and reduce the switching loss. The technical scheme adopted by the invention is as follows: the IGBT device with low switching loss comprises a heavily doped P region, a field cut-off region and an N-type drift region which are sequentially arranged from bottom to top; The N-type drift region is divided into a first region and a second region adjacent to the first region, a carrier storage layer is formed on the first region of the N-type drift region, a deep P region is formed on the second region and extends downwards to the inside of the N-type drift region, the top of the carrier storage layer is flush with the top of the deep P region, a P-type body region is formed on the carrier storage layer, a P+ emitter region and a P+ contact region are formed on the P-type body region in the same layer, and the carrier storage layer, the deep P region, the P-type body region, the N+ emitter region and the P+ contact region jointly form a surface source layer region structure; an interlayer dielectric layer and a top metal electrode are sequentially formed on the surface source layer region structure, and a contact hole which longitudinally penetrates through the interlayer dielectric layer is formed on the interlayer dielect