CN-122028448-A - Semiconductor device, method of manufacturing the same, and electronic apparatus

Abstract

The application provides a semiconductor device, a manufacturing method thereof and electronic equipment. The manufacturing method of the semiconductor device comprises the steps of forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of first dielectric layers and a plurality of first insulating layers which are alternately stacked, the stacked structure is provided with a plurality of first grooves which are arranged along a first direction at intervals and first grooves which are arranged along the first direction in a same layer with the first insulating layers, the first grooves and the first grooves are communicated and extend along a second direction, the first directions intersect with the second direction and are parallel to the substrate, catalytic liquid drops are formed at the end parts of the first grooves along the second direction, a semiconductor layer which covers the outer surface of the catalytic liquid drops and the inner surface of the first grooves is deposited, and the catalytic liquid drops are moved along the second direction based on an annealing process to induce the semiconductor layer to react to form the semiconductor structure of the transistor. The embodiment of the application can effectively improve the performance of the semiconductor device.

Inventors

• LIU XIAOMENG
• LIU XINYOU
• WANG XIANGSHENG
• WANG GUILEI
• ZHAO CHAO

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241112

Claims (11)

1. 1. A method of manufacturing a semiconductor device, comprising: Forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of first dielectric layers and a plurality of first insulating layers which are alternately stacked, and the stacked structure is provided with a plurality of first grooves which are arranged along a first direction at intervals and first grooves which are arranged along the same layer as the first insulating layers, wherein the first grooves are communicated with the first grooves and extend along a second direction, and the first direction is intersected with the second direction and is parallel to the substrate; Forming catalytic droplets in the first grooves along the ends of the second direction; depositing a semiconductor layer covering the outer surface of the catalytic liquid drop and the inner surface of the first groove; the catalytic droplet is caused to move in the second direction based on an annealing process, and the semiconductor layer is induced to react to form a semiconductor structure of the transistor.
2. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor structure comprises at least one of single crystal silicon, single crystal germanium, or silicon germanium.
3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein forming a catalytic droplet in an end portion of the first groove in the second direction includes: depositing a catalyst layer in the first trench and the first recess of a first region, the first region being at an end of the stacked structure in the second direction; the catalyst layer is condensed into catalytic droplets based on a plasma treatment technique, the catalytic droplets being located in the first region.
4. 4. The method for manufacturing a semiconductor device according to claim 3, wherein a material of the catalyst layer includes at least one of indium, gold, nickel, iron, or aluminum.
5. 5. A method for manufacturing a semiconductor device according to claim 3, wherein the plasma employed in the plasma treatment technique is formed of hydrogen gas.
6. 6. The method for manufacturing a semiconductor device according to claim 3, wherein depositing a catalyst layer in the first trench and the first groove of the first region comprises: filling a first sacrificial layer in the first groove and the first groove; Removing the first sacrificial layer in the first groove and the first groove of the first region; Depositing a catalyst layer within the first trench and within the first recess of the first region; And removing the catalyst layer at the bottom of the first groove.
7. 7. The method for manufacturing a semiconductor device according to claim 1, wherein depositing a semiconductor layer that covers an outer surface of the catalytic droplet and an inner surface of the first recess, comprises: Depositing a layer of semiconductor material within the first trench and the first recess such that the layer of semiconductor material covers the catalytic droplet outer surface and the first recess inner surface; and removing the semiconductor material layer in the first groove to form the semiconductor layer.
8. 8. The method according to claim 1, wherein after moving the catalytic droplet in the second direction based on an annealing process to induce the semiconductor layer to react to form a semiconductor structure of a transistor, further comprising: Doping the semiconductor structures of the second region and the third region to form a first source drain electrode and a second source drain electrode respectively; and forming a gate dielectric structure and a gate electrode on the periphery of the semiconductor structure of the fourth region in sequence to form a transistor, wherein the second region, the fourth region and the third region are sequentially arranged along the second direction.
9. 9. A semiconductor device, comprising: and each transistor comprises a semiconductor structure extending along a second direction, wherein the semiconductor structure is obtained by catalyzing liquid drop movement induction semiconductor layers based on an annealing process.
10. 10. The semiconductor device according to claim 9, wherein the transistor further comprises: the first source drain electrode and the second source drain electrode are respectively formed by the semiconductor structure positioned in the second region and the semiconductor structure positioned in the third region; the grid dielectric structure and the grid electrode sequentially encircle the periphery of the semiconductor structure in the fourth region; the second region, the fourth region and the third region are sequentially arranged along the second direction.
11. 11. An electronic apparatus comprising a semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 8, or a semiconductor device according to any one of claims 9 to 10.

Description

Semiconductor device, method of manufacturing the same, and electronic apparatus Technical Field The application relates to the technical field of semiconductor devices, in particular to a semiconductor device, a manufacturing method thereof and electronic equipment. Background With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the variety and number of semiconductor devices included in a single chip are increasing, so that any minor differences in process production may affect the performance of the semiconductor devices. In order to reduce the cost of the product as much as possible, it is desirable to make as many semiconductor devices as possible on a substrate of limited area. Since moore's law emerged, the industry has proposed structural designs and process optimization for various semiconductor devices to meet the needs of current products. Disclosure of Invention The application provides a semiconductor device, a manufacturing method thereof and electronic equipment, aiming at the defects of the prior mode, and the performance of the semiconductor device can be effectively improved. In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including: forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of first dielectric layers and a plurality of first insulating layers which are alternately stacked, and is provided with a plurality of first grooves which are arranged along a first direction at intervals and first grooves which are arranged on the same layer as the first insulating layers, wherein the first grooves and the first grooves are communicated and extend along a second direction, and the first direction is intersected with the second direction and is parallel to the substrate; Forming catalytic droplets in the first grooves at the ends in the second direction; depositing a semiconductor layer covering the outer surface of the catalytic liquid drop and the inner surface of the first groove; the catalytic droplet is caused to move in a second direction based on the annealing process, inducing the semiconductor layer to react to form a semiconductor structure of the transistor. In some possible embodiments, the semiconductor structure comprises at least one of monocrystalline silicon, monocrystalline germanium, or silicon germanium. In some possible embodiments, forming catalytic droplets in the end of the first groove in the second direction includes: Depositing a catalyst layer in the first trench and the first groove of the first region, the first region being located at an end of the stacked structure in the second direction; The catalyst layer is condensed into catalytic droplets based on a plasma treatment technique, the catalytic droplets being located in the first region. In some possible embodiments, the material of the catalyst layer comprises at least one of indium, gold, nickel, iron, or aluminum. In some possible embodiments, the plasma employed in the plasma processing technique is formed from hydrogen. In some possible embodiments, depositing a catalyst layer within the first trench and the first groove of the first region comprises: Filling a first sacrificial layer in the first groove and the first groove; Removing the first sacrificial layer in the first groove and the first groove of the first region; Depositing a catalyst layer in the first trench and in the first recess of the first region; and removing the catalyst layer at the bottom of the first groove. In some possible embodiments, depositing a semiconductor layer that covers the outer surface of the catalytic droplet and the inner surface of the first recess comprises: Depositing a layer of semiconductor material within the first trench and the first recess such that the layer of semiconductor material covers the outer surface of the catalytic droplet and the inner surface of the first recess; And removing the semiconductor material layer in the first groove to form the semiconductor layer. In some possible embodiments, after the catalytic droplet is moved in the second direction based on the annealing process to induce the semiconductor layer to react to form the semiconductor structure of the transistor, further comprising: Doping the semiconductor structures of the second region and the third region to form a first source drain electrode and a second source drain electrode respectively; And sequentially forming a gate dielectric structure and a gate on the periphery of the semiconductor structure of the fourth region to form a transistor, wherein the second region, the fourth region and the third region are sequentially arranged along the second direction. In a second aspect, the embodiment of the application also provides a semiconductor device, which comprises a plurality of layers of transistors, wherein each layer of transistors com