CN-122028449-A - Shielded gate trench MOSFET device and method of making same

CN122028449ACN 122028449 ACN122028449 ACN 122028449ACN-122028449-A

Abstract

The application provides a shielded gate trench MOSFET device and a preparation method thereof, wherein in the preparation method, an epitaxial layer is etched firstly to form a first trench, then a first oxide layer is formed on the side wall of the first trench, then the epitaxial layer is etched continuously to form a second trench, then ion implantation is carried out on the bottom wall and part of the side wall of the second trench to form an ion implantation region, then a thermal annealing process is carried out to convert the ion implantation region into an ion diffusion region, finally the epitaxial layer is etched continuously to form a third trench, and finally a second oxide layer is formed on the side wall and the bottom wall of the third trench. According to the application, impurities are doped from the side wall of the channel to the middle section of the drift region by adding one ion implantation process in three-step groove etching, so that the electric field distribution in the depletion layer of the device can be optimized, the electric field intensity in the middle section of the MESA region is raised, the on-resistance of the drift region can be reduced, the thickness of the depletion layer can be reduced, the electric field intensity at the bottom of the third groove is reduced, and the breakdown voltage of the device is raised.

Inventors

HU JIANING
SUN WENZHEN

Assignees

华虹半导体制造(无锡)有限公司

Dates

Publication Date: 20260512
Application Date: 20260107

Claims (10)

1. The preparation method of the shielded gate trench MOSFET device is characterized by comprising the following steps of: providing a substrate, wherein an epitaxial layer and a hard mask layer are sequentially formed on the substrate, and an opening is formed in the hard mask layer; Etching the epitaxial layer with the first thickness by taking the hard mask layer as a mask so as to form a first groove in the epitaxial layer; forming a first oxide layer, wherein the first oxide layer covers the side wall and the bottom wall of the first groove; Continuing to etch the first oxide layer at the bottom of the first trench and the epitaxial layer with the second thickness downwards by taking the hard mask layer as a mask so as to form a second trench; Ion implantation is carried out on the bottom wall of the second groove and the side wall of the second groove which is not covered by the first oxide layer, so that an ion implantation area is formed; performing a thermal annealing process on the semiconductor structure after the ion implantation process, wherein the ion implantation region diffuses to a certain depth into the epitaxial layer outside the second trench at the moment so as to form an ion diffusion region; continuing to etch the epitaxial layer with the third thickness at the bottom of the second trench downwards by taking the hard mask layer as a mask so as to form a third trench; A second oxide layer is formed overlying the first oxide layer on the sidewalls of the third trench, and the bottom wall and remaining sidewalls of the third trench.
2. The method of fabricating a shielded gate trench MOSFET device of claim 1 wherein the etched third thickness of the epitaxial layer is greater than a diffusion depth of the ion diffusion region at the bottom of the second trench.
3. The method of manufacturing a shielded gate trench MOSFET device of claim 1, wherein a ratio of a lateral dimension of the ion diffusion region outside the second trench sidewall to a lateral dimension of the second trench is (1:5) - (5:1).
4. The method of manufacturing a shielded gate trench MOSFET device of claim 1, wherein the ratio of the etched first thickness, second thickness, and third thickness of the epitaxial layer is 1:3:1.
5. The method of manufacturing a shielded gate trench MOSFET device of claim 1, wherein the first oxide layer has a thickness that is one-fourth the thickness of the second oxide layer.
6. The method of claim 1, wherein the step of ion implanting the bottom wall of the second trench and the sidewall of the second trench not covered by the first oxide layer to form an ion implanted region comprises: And performing N-type ion implantation on the bottom wall of the second groove and the side wall of the second groove which is not covered by the first oxide layer to form an N-type ion implantation region.
7. The method for manufacturing a shielded gate trench MOSFET device of claim 1, wherein the hard mask layer is silicon nitride.
8. The method of manufacturing a shielded gate trench MOSFET device of claim 1, wherein the doping type of the conductive ions in the substrate is N-type.
9. The method of manufacturing a shielded gate trench MOSFET device of claim 1, wherein the doping type of the conductive ions in the epitaxial layer is N-type.
10. A shielded gate trench MOSFET device prepared based on the method of preparing a shielded gate trench MOSFET device according to any one of claims 1-9, comprising: The substrate is sequentially provided with an epitaxial layer and a hard mask layer, and an opening is formed in the hard mask layer; a third trench in the epitaxial layer; a first oxide layer covering a portion of a sidewall of the third trench near a top end of the third trench; The ion diffusion region is positioned in the epitaxial layer outside the side wall of the third groove, and the vertical dimension of the ion diffusion region is smaller than the depth of the third groove; And a second oxide layer covering the first oxide layer on the side wall of the third trench, and the bottom wall and the remaining side wall of the third trench.

Description

Shielded gate trench MOSFET device and method of making same Technical Field The application relates to the technical field of semiconductor manufacturing, in particular to a shielded gate trench MOSFET device and a preparation method thereof. Background In a reverse off state of a shielded gate trench MOSFET (SGT-MOSFET) device, the electric field distribution of the MESA region is catenary, the fully depleted drift region will typically exhibit two electric field peaks along the silicon substrate/trench gate oxide interface, the first peak occurring at the PN junction formed by the P-type body region and the N-type drift region, the other peak occurring at the bottom of the trench gate oxide (near the bottom of the trench), while most of the distance in the middle of the depletion region produces a low electric field. The MESA region refers to a raised region between trenches in a cell structure of the device, and is a key carrier of a core functional layer (such as a gate, a source and a body) of the device, so as to directly determine on-resistance, voltage-resistance and switching characteristics of the device. Because the electric field intensity at two ends of the catenary is higher, the whole drift region must maintain a lower doping concentration to prevent breakdown at two ends, so the on-resistance of the drift region is large. In order to obtain better electric field distribution in the depletion region, related researchers in the field currently propose to use methods such as drift region doped gradually, slope side oxygen and multi-step side oxygen to improve the electric field distribution of the depletion region, but the requirements of the methods on the process are higher, and the corresponding manufacturing difficulty is also higher. Disclosure of Invention The application provides a shielded gate trench MOSFET device and a preparation method thereof, which can solve the problems of larger on-resistance of a drift region and even breakdown of the device caused by over-concentrated electric field distribution at certain positions of the drift region in the conventional shielded gate trench MOSFET device. In one aspect, an embodiment of the present application provides a method for manufacturing a shielded gate trench MOSFET device, including: providing a substrate, wherein an epitaxial layer and a hard mask layer are sequentially formed on the substrate, and an opening is formed in the hard mask layer; Etching the epitaxial layer with the first thickness by taking the hard mask layer as a mask so as to form a first groove in the epitaxial layer; forming a first oxide layer, wherein the first oxide layer covers the side wall and the bottom wall of the first groove; Continuing to etch the first oxide layer at the bottom of the first trench and the epitaxial layer with the second thickness downwards by taking the hard mask layer as a mask so as to form a second trench; Ion implantation is carried out on the bottom wall of the second groove and the side wall of the second groove which is not covered by the first oxide layer, so that an ion implantation area is formed; performing a thermal annealing process on the semiconductor structure after the ion implantation process, wherein the ion implantation region diffuses to a certain depth into the epitaxial layer outside the second trench at the moment so as to form an ion diffusion region; continuing to etch the epitaxial layer with the third thickness at the bottom of the second trench downwards by taking the hard mask layer as a mask so as to form a third trench; A second oxide layer is formed overlying the first oxide layer on the sidewalls of the third trench, and the bottom wall and remaining sidewalls of the third trench. Optionally, in the method for manufacturing the shielded gate trench MOSFET device, the third thickness of the etched epitaxial layer is greater than the diffusion depth of the ion diffusion region at the bottom of the second trench. Optionally, in the method for manufacturing a shielded gate trench MOSFET device, a ratio of a lateral dimension of the ion diffusion region outside the sidewall of the second trench to a lateral dimension of the second trench is (1:5) - (5:1). Optionally, in the method for manufacturing the shielded gate trench MOSFET device, a ratio of the first thickness, the second thickness, and the third thickness of the etched epitaxial layer is 1:3:1. Optionally, in the method for manufacturing the shielded gate trench MOSFET device, the thickness of the first oxide layer is one fourth of the thickness of the second oxide layer. Optionally, in the method for manufacturing a shielded gate trench MOSFET device, the step of performing ion implantation on the bottom wall of the second trench and the sidewall of the second trench not covered by the first oxide layer to form an ion implantation region includes: And performing N-type ion implantation on the bottom wall of the second groove and the side wall o