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CN-122028450-A - Method for improving reliability of lateral diffusion metal oxide semiconductor

CN122028450ACN 122028450 ACN122028450 ACN 122028450ACN-122028450-A

Abstract

The present invention provides a method for improving the reliability of a laterally diffused metal oxide semiconductor. The method comprises the steps of providing a P-type semiconductor substrate, defining a drift region and a well region in the substrate, performing ion implantation by adopting a P-type heavily doped element to define a P-type body region, defining a gate structure on the surface of the substrate, and defining a source-drain contact region. According to the invention, the heavily doped elements such as indium and aluminum are adopted to replace boron for P-type body region injection, the junction depth and transverse diffusion are effectively controlled by utilizing the low diffusion capability and steep doping characteristics of the heavily doped elements, the drift region length is kept, meanwhile, the surface electric field peak value is reduced, the electric field distribution is optimized, the hot carrier injection problem is relieved, and the reliability service life of the LDMOS device is remarkably prolonged.

Inventors

  • ZHENG YUN
  • PENG JIAQI
  • CHEN YONG
  • WANG LI
  • CHEN HUALUN

Assignees

  • 华虹半导体(无锡)有限公司
  • 华虹半导体制造(无锡)有限公司
  • 上海华虹宏力半导体制造有限公司

Dates

Publication Date
20260512
Application Date
20260107

Claims (11)

  1. 1. A method for improving reliability of a laterally diffused metal oxide semiconductor comprising at least: step one, providing a P-type semiconductor substrate; Step two, defining a drift region and a well region in the P-type semiconductor substrate through photoetching and ion implantation processes; defining a P-type body region in the P-type semiconductor substrate through photoetching and ion implantation processes, wherein the ion implantation process adopts a P-type heavily doped element for implantation; step four, defining a grid structure on the surface of the P-type semiconductor substrate through film deposition, photoetching and etching processes; And fifthly, defining a source-drain contact region in the P-type semiconductor substrate through photoetching and ion implantation processes.
  2. 2. The method of claim 1, wherein in the step one, the forming of the P-type semiconductor base comprises providing a P-type substrate, defining an N-type buried layer on a surface of the P-type substrate, and growing an epitaxial layer on the P-type substrate as a P-type epitaxial layer.
  3. 3. The method of claim 2, wherein in the step one, the defining the N-type buried layer comprises defining a photoresist pattern on the surface of the P-type substrate, and defining the N-type buried layer as an isolation layer at the bottom of the device by using an opening of the patterned photoresist layer.
  4. 4. The method of claim 1, wherein in the step two, before the step of defining the drift region and the well region, shallow trench isolation structures are formed in the P-type semiconductor substrate by photolithography, etching and filling processes to define the active region.
  5. 5. The method of claim 1, wherein in the second step, the drift region comprises an N-type drift region or a P-type drift region, and the well region comprises an N-type well or a P-type well.
  6. 6. The method of claim 1, wherein in step three, the P-type heavily doped element is selected from the group consisting of group III metal elements.
  7. 7. The method of improving reliability of a laterally diffused metal oxide semiconductor according to claim 6, wherein in the third step, the group III metal element is indium or aluminum.
  8. 8. The method of claim 1, wherein in the third step, the ion implantation process comprises an implantation energy of 50-800 keV and an implantation dose of 1E12-9E16 atoms/cm2.
  9. 9. The method of claim 1, wherein in step three, the P-type heavily doped element has a lower diffusion coefficient and a higher activation energy than boron.
  10. 10. The method of claim 1, wherein in step four, the gate structure comprises a gate dielectric layer and a gate polysilicon.
  11. 11. The method of claim 1, wherein in step five, the source drain contact region comprises an N-type heavily doped region and a P-type heavily doped region, and wherein after step five, the method further comprises defining a silicide blocking layer, a contact hole and a metal layer to form a BCD device.

Description

Method for improving reliability of lateral diffusion metal oxide semiconductor Technical Field The invention relates to the technical field of semiconductors, in particular to a method for improving reliability of a lateral diffusion metal oxide semiconductor. Background Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices are currently widely used in scenes where reliability requirements are extremely high, such as automotive electronics, due to their excellent high frequency, high voltage endurance capabilities. In characterizing the performance of an LDMOS device, breakdown Voltage (BV), on-Resistance (RSP), and Safe Operating Area (SOA) are three core indicators. In device design and fabrication, a compromise between the three criteria is often required to obtain optimal overall performance. In general, a high voltage LDMOS device integrated in a BCD (Bipolar-CMOS-DMOS) process needs to operate in a high voltage environment, which generates a high electric field inside the device, resulting in Hot Carrier Injection (HCI) gate oxide. The hot carrier effect can cause problems such as drift of threshold voltage of the device, reduction of transconductance and the like, and the reliability service life of the device is seriously affected. In the conventional LDMOS manufacturing process, a P-type body (Pbody) is mainly implanted with Boron (Boron, B) element. However, the diffusion rate of boron element in the silicon lattice is relatively high, and significant lateral diffusion easily occurs in the subsequent high temperature process. The lateral diffusion characteristic which is not easy to control is easy to squeeze the drift region length and change the junction depth, so that the breakdown voltage stability of the device is directly affected. In addition, the traditional boron doping process is difficult to accurately regulate and control the surface electric field distribution, so that the electric field peak value is higher, and the reliability problem caused by hot carrier injection is further aggravated. Therefore, there is a need in the art for an LDMOS fabrication method that can effectively control junction depth and lateral diffusion, while reducing surface electric field peaks and improving device reliability. Disclosure of Invention The invention aims to solve the technical problems that in a Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device, a traditional P-type body region is usually implanted with boron, the lateral diffusion is easy to form due to the high diffusion speed of boron, the length and junction depth of a drift region are difficult to precisely control, so that the breakdown voltage is influenced, and meanwhile, a high electric field generated in a high-voltage environment can cause hot carriers to be implanted into gate oxide, so that the reliability life of the device is influenced. In view of this, the present invention provides a method for improving the reliability of a laterally diffused metal oxide semiconductor, which aims to improve the reliability of a device by optimizing the implantation process of a P-type body region, precisely controlling the junction depth and lateral diffusion, and optimizing the electric field distribution. The invention provides a method for improving the reliability of a lateral diffusion metal oxide semiconductor, which comprises the following steps: step one, providing a P-type semiconductor substrate; Step two, defining a drift region and a well region in the P-type semiconductor substrate through photoetching and ion implantation processes; defining a P-type body region in the P-type semiconductor substrate through photoetching and ion implantation processes, wherein the ion implantation process adopts a P-type heavily doped element for implantation; step four, defining a grid structure on the surface of the P-type semiconductor substrate through film deposition, photoetching and etching processes; And fifthly, defining a source-drain contact region in the P-type semiconductor substrate through photoetching and ion implantation processes. Preferably, in the first step, the forming process of the P-type semiconductor base comprises providing a P-type substrate, defining an N-type buried layer on the surface of the P-type substrate, and growing an epitaxial layer on the P-type substrate to serve as a P-type epitaxial layer. Preferably, in the first step, the process of defining the N-type buried layer specifically includes defining a photoresist pattern on the surface of the P-type substrate, and defining the N-type buried layer by using an opening of the patterned photoresist layer, where the N-type buried layer is used as an isolation layer at the bottom of the device. Preferably, before the defining of the drift region and the well region in the second step, a shallow trench isolation structure is formed in the P-type semiconductor substrate through photolithography, etching and filling processes, and is used for defini