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CN-122028451-A - Technological method applied to MOS device manufacture

CN122028451ACN 122028451 ACN122028451 ACN 122028451ACN-122028451-A

Abstract

The application discloses a process method applied to manufacturing of a Metal Oxide Semiconductor (MOS) device, which comprises the steps of forming a polycrystalline silicon layer on a gate dielectric layer, forming a gate dielectric layer on a substrate, forming an oxide layer on the polycrystalline silicon layer through a metal oxide semiconductor (TEOS) deposition process, repairing the surface morphology of the polycrystalline silicon layer to improve the uniformity of the surface of the polycrystalline silicon layer, covering a photoresist on the oxide layer, removing the photoresist of a target area through exposure and development in sequence to expose the oxide layer of the target area, and performing ion implantation on the polycrystalline silicon layer of the target area to inhibit the depletion effect of the polycrystalline silicon gate when the MOS device works. According to the application, the oxide layer is formed on the polysilicon layer through the TEOS deposition process to repair the surface morphology of the polysilicon layer, so that the uniformity of the surface of the polysilicon layer is improved, the uniformity of the distribution of impurities in the polysilicon layer after the subsequent ion implantation is improved, the depletion effect is improved, and the fluctuation of the threshold voltage of the device is reduced.

Inventors

  • CHEN ZHIWEI
  • WU BOWEN
  • MI KUI
  • LI KUNLE
  • PENG YUFEI
  • CAO ZIGUI

Assignees

  • 华虹半导体制造(无锡)有限公司

Dates

Publication Date
20260512
Application Date
20260116

Claims (7)

  1. 1. The process method applied to manufacturing the MOS device is characterized by comprising the following steps of: Forming a polysilicon layer on the gate dielectric layer, wherein the gate dielectric layer is formed on the substrate, and the polysilicon layer is used for forming a polysilicon gate of the MOS device; Forming an oxide layer on the polycrystalline silicon layer through a TEOS deposition process, wherein the oxide layer is used for repairing the surface morphology of the polycrystalline silicon layer and improving the uniformity of the surface of the polycrystalline silicon layer; covering a photoresist on the oxide layer, and sequentially removing the photoresist of the target area through exposure and development to expose the oxide layer of the target area; and carrying out ion implantation on the polysilicon layer of the target area to inhibit the depletion effect of the polysilicon gate when the MOS device works.
  2. 2. The method of claim 1, wherein after forming an oxide layer on the polysilicon layer by a TEOS deposition process, the oxide layer has a thickness of 50 a to 200 a.
  3. 3. The method of claim 2, wherein the polysilicon layer has a thickness of 800 angstroms to 2000 angstroms.
  4. 4. A method according to any one of claims 1 to 3, characterized in that during the formation of the oxide layer on the polysilicon layer by means of a TEOS deposition process, 4 to 6 g of TEOS is introduced.
  5. 5. The method of claim 4, wherein a flow rate of the carrier gas is 3000SCCM to 5000SCCM during the forming of the oxide layer on the polysilicon layer by the TEOS deposition process.
  6. 6. The method of claim 5, wherein the temperature in the reaction chamber is 350 degrees celsius to 450 degrees celsius during the forming of the oxide layer on the polysilicon layer by the TEOS deposition process.
  7. 7. The method of claim 6, wherein the pressure in the reaction chamber is between 4 torr and 6 torr during the formation of the oxide layer on the polysilicon layer by the TEOS deposition process.

Description

Technological method applied to MOS device manufacture Technical Field The application relates to the technical field of semiconductor devices and integrated circuits, in particular to a process method applied to manufacturing of MOS devices. Background Metal-oxide-semiconductor field effect transistor (MOSFET) devices, referred to herein simply as "MOS") devices, are electronic devices that are widely used in analog and digital circuits. The following describes the state of an N-type MOS (NMOS) device in operation, taking the NMOS device as an example: Referring to fig. 1, a schematic cross-sectional view of an NMOS device in an operating state is shown. As shown in fig. 1, a gate dielectric layer 120 is formed on a substrate 110, a polysilicon gate 130 is formed on the gate dielectric layer 120, wherein P (positive) type impurities are doped in the substrate 110, N type impurities are doped in the polysilicon gate 130, when a voltage is applied to the polysilicon gate 130, the polysilicon gate 130 attracts free electrons in the substrate 110 to a region above the substrate 210 near the gate dielectric layer 120, forming an inversion layer 1101, and at the same time, carriers of opposite conductivity type are collected in a region near the gate dielectric layer 120 in the polysilicon gate 130, forming a polysilicon depletion layer 1301 to maintain electrical neutrality. This charge accumulation process will deplete the charge of the nearby semiconductor, and when the charge in the semiconductor is fully depleted, the semiconductor device will be nearly identical to an insulator, equivalent to an increase in the equivalent thickness (equivalent oxide thickness, EOT) of the gate dielectric layer. In view of this, a polysilicon gate pre-doping process is proposed in the related art to suppress the polysilicon depletion effect (poly depletion effect, PDE) and reduce the equivalent thickness of the gate dielectric layer. However, taking an NMOS device as an example, in the pre-doping process of the polysilicon gate, phosphorus (P) is used as a doping source, and phosphorus is unevenly distributed in the polysilicon, so that polysilicon depletion is formed near the gate dielectric, thereby causing the threshold voltage of the NMOS device to fluctuate greatly and reducing the electrical performance of the device. Disclosure of Invention The application provides a process method applied to MOS device manufacture, which can solve the problem of larger threshold voltage fluctuation of MOS devices in the related technology, and comprises the following steps: Forming a polysilicon layer on the gate dielectric layer, wherein the gate dielectric layer is formed on the substrate, and the polysilicon layer is used for forming a polysilicon gate of the MOS device; Forming an oxide layer on the polycrystalline silicon layer through a TEOS deposition process, wherein the oxide layer is used for repairing the surface morphology of the polycrystalline silicon layer and improving the uniformity of the surface of the polycrystalline silicon layer; covering a photoresist on the oxide layer, and sequentially removing the photoresist of the target area through exposure and development to expose the oxide layer of the target area; and carrying out ion implantation on the polysilicon layer of the target area to inhibit the depletion effect of the polysilicon gate when the MOS device works. In some embodiments, the oxide layer is 50 to 200 angstroms thick after forming the oxide layer on the polysilicon layer by a TEOS deposition process. In some embodiments, the polysilicon layer has a thickness of 800 angstroms to 2000 angstroms. In some embodiments, the TEOS is introduced during the formation of the oxide layer on the polysilicon layer by a TEOS deposition process at 4 grams to 6 grams. In some embodiments, the flow rate of the carrier gas is 3000SCCM to 5000SCCM during the formation of the oxide layer on the polysilicon layer by the TEOS deposition process. In some embodiments, the temperature within the reaction chamber is between 350 degrees celsius and 450 degrees celsius during the forming of the oxide layer on the polysilicon layer by the TEOS deposition process. In some embodiments, the pressure within the reaction chamber is between 4 torr and 6 torr during the formation of the oxide layer on the polysilicon layer by the TEOS deposition process. The technical scheme of the application at least comprises the following advantages: In the manufacturing process of the MOS device, before the pre-doping of the polysilicon layer, an oxide layer is formed on the polysilicon layer through a TEOS deposition process to repair the surface morphology of the polysilicon layer, so that the uniformity of the surface of the polysilicon layer is improved, the uniformity of the distribution of impurities in the polysilicon layer after the subsequent ion implantation is improved, the depletion effect is improved, and the fluctuation of the thr