CN-122028452-A - Two-dimensional semiconductor FET based on autoxidation p-type doping and preparation method thereof

Abstract

The invention discloses a two-dimensional semiconductor FET based on autoxidation p-type doping and a preparation method thereof, wherein the preparation method comprises the steps of firstly preparing a source electrode and a drain electrode on the surface of a two-dimensional semiconductor material, defining a two-dimensional semiconductor channel region, then autoxidizing the exposed two-dimensional semiconductor channel region by utilizing a plasma treatment process to form a p-type doping layer, preparing a seed crystal layer, growing a gate dielectric layer, and finally preparing a top gate; according to the invention, the exposed two-dimensional semiconductor channel is treated through a plasma treatment process, so that the surface layer of the semiconductor channel is subjected to autoxidation to realize a p-type doped layer, and a seed crystal layer is prepared on the p-type doped layer to assist in growing the gate dielectric layer.

Inventors

• BAO WENZHONG

Assignees

• 原集微科技(上海)有限公司

Dates

Publication Date

20260512

Application Date

20260123

Claims (10)

1. 1. A method for fabricating a two-dimensional semiconductor FET based on autoxidation p-type doping, comprising: s1, preparing a source electrode and a drain electrode on the surface of a two-dimensional semiconductor material; S2, defining a two-dimensional semiconductor channel region by an etching process; s3, autoxidizing the exposed two-dimensional semiconductor channel region by utilizing a plasma treatment process to form a p-type doped layer, wherein the thickness of the p-type doped layer is smaller than the total thickness of the two-dimensional semiconductor channel; s4, preparing a seed crystal layer, wherein the seed crystal layer covers the whole area of the two-dimensional semiconductor FET; s5, growing a gate dielectric layer on the surface of the seed crystal layer; S6, preparing a grid electrode on the surface of the grid dielectric layer.
2. 2. The method according to claim 1, wherein in step S1, the source electrode and the drain electrode are formed by a metal deposition process, and the source electrode and the drain electrode are made of gold, platinum, palladium, ruthenium, antimony, bismuth, aluminum, indium, nickel or titanium; the number of layers of the two-dimensional semiconductor material is at least two.
3. 3. The method of claim 1, wherein the etching process in step S2 is a capacitively coupled plasma etching process or an inductively coupled plasma etching process using a plasma containing F + , ar or O 2 for removing two-dimensional semiconductor material outside the two-dimensional semiconductor channel.
4. 4. The method of claim 1, wherein in step S3, the plasma treatment process is a capacitive plasma etching process or an inductively coupled plasma etching process, and the gas used is oxygen.
5. 5. The method of claim 1, wherein the thickness of the p-doped layer is 1-2nm.
6. 6. The method according to claim 1, wherein the seed layer in step S4 is prepared by one of chemical vapor deposition or physical vapor deposition, and the seed layer is made of one of silicon oxide, aluminum oxide, yttrium oxide, antimony oxide or gadolinium oxide.
7. 7. The method of claim 1, wherein the seed layer has a thickness of 1-4nm.
8. 8. The method of claim 1, wherein the gate dielectric layer in step S5 is formed by one of atomic layer deposition, chemical vapor deposition or physical vapor deposition, and the gate dielectric layer is formed by one of tantalum oxide, yttrium oxide, zirconium oxide, hafnium oxide, aluminum oxide or aluminum nitride.
9. 9. The method of claim 1, wherein the process for fabricating the gate electrode in step S6 is a metal deposition process, and the gate electrode is made of one of gold, platinum, palladium, ruthenium, antimony, bismuth, aluminum, indium, nickel or titanium.
10. 10. A two-dimensional semiconductor top-gate field effect transistor prepared by the method of preparing a two-dimensional semiconductor top-gate field effect transistor as claimed in any one of claims 1 to 9.

Description

Two-dimensional semiconductor FET based on autoxidation p-type doping and preparation method thereof Technical Field The invention relates to the technical field of semiconductor device preparation, in particular to a two-dimensional semiconductor FET based on autoxidation p-type doping and a preparation method thereof. Background In the last decades, as transistor sizes have been reduced, the scale of integrated circuits has also been increasing. However, as the dimensions of silicon-based transistors approach physical limits, transistor scaling encounters bottlenecks. Two-dimensional (2D) materials show great potential in scaling and avoiding short channel effects due to their ultra-thin thickness and lack of dangling bonds. In Complementary Metal Oxide Semiconductor (CMOS) technology, it is important to precisely control and match the polarity (n-type or p-type) of the transistor. However, field Effect Transistors (FETs) based on two-dimensional Transition Metal Disulfides (TMDCs) mainly exhibit N-type transport behavior, and the lack of high performance P-type two-dimensional semiconductor transistors is a major challenge for the trend of two-dimensional materials towards application. WSe 2 is a promising 2D bipolar semiconductor with a bandgap intermediate arrangement contacting the metal fermi level closer to the valence band edge, which allows high performance P-type field effect transistors to be obtained with appropriate doping strategies, however, current doping approaches face challenges such as limited doping efficiency and gradual degradation of electrical properties due to surface adsorption instability. In addition, the ultra-thin nature of the single layer of two-dimensional material makes its performance extremely sensitive to changes in its lattice structure, resulting in reduced device uniformity and yield. Therefore, developing a high-performance P-type two-dimensional semiconductor top gate field effect transistor and a preparation method thereof is a feasible path for pushing the two-dimensional semiconductor transistor to develop towards industrialization. Disclosure of Invention The invention aims to provide a two-dimensional semiconductor FET based on autoxidation P-type doping and a preparation method thereof, wherein a plasma treatment process is adopted to enable the surface layer of an exposed two-dimensional semiconductor channel to be autoxidized to generate a P-type doping layer, and a seed crystal layer is prepared on the P-type doping layer to assist in growing a gate dielectric layer, so that the high-performance P-type two-dimensional semiconductor transistor is finally obtained. In order to solve the above technical problem, a first aspect of the present invention provides a method for preparing a two-dimensional semiconductor FET based on autoxidation p-type doping, comprising: s1, preparing a source electrode and a drain electrode on the surface of a two-dimensional semiconductor material; S2, defining a two-dimensional semiconductor channel region by an etching process; s3, autoxidizing the exposed two-dimensional semiconductor channel region by utilizing a plasma treatment process to form a p-type doped layer, wherein the thickness of the p-type doped layer is smaller than the total thickness of the two-dimensional semiconductor channel; s4, preparing a seed crystal layer, wherein the seed crystal layer covers the whole area of the two-dimensional semiconductor FET; s5, growing a gate dielectric layer on the surface of the seed crystal layer; S6, preparing a grid electrode on the surface of the grid dielectric layer. Preferably, in step S1, the source electrode and the drain electrode are prepared by a metal deposition process, and the source electrode and the drain electrode are made of gold, platinum, palladium, ruthenium, antimony, bismuth, aluminum, indium, nickel or titanium; the number of layers of the two-dimensional semiconductor material is at least two. Preferably, the etching process in step S2 is a capacitively coupled plasma etching process or an inductively coupled plasma etching process using a plasma containing F +, ar or O 2 for removing two-dimensional semiconductor material outside the two-dimensional semiconductor channel. Preferably, in step S3, the plasma treatment process uses a capacitive plasma etching process or an inductively coupled plasma etching process, and the gas used is oxygen. Preferably, the thickness of the p-type doped layer is 1-2nm. Preferably, the preparation process of the seed crystal layer in the step S4 is one of a chemical vapor deposition process or a physical vapor deposition process, and the seed crystal layer is made of one of silicon oxide, aluminum oxide, yttrium oxide, antimony oxide or gadolinium oxide. Preferably, the seed layer has a thickness of 1-4nm. Preferably, the gate dielectric layer in step S5 is prepared by one of an atomic layer deposition process, a chemical vapor deposition process or a physical vapo