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CN-122028453-A - Two-dimensional semiconductor top gate field effect transistor and preparation method thereof

CN122028453ACN 122028453 ACN122028453 ACN 122028453ACN-122028453-A

Abstract

The invention discloses a two-dimensional semiconductor top gate field effect transistor and a preparation method thereof, wherein the preparation method comprises the steps of preparing a source electrode and a drain electrode on the surface of a two-dimensional semiconductor material, defining a two-dimensional semiconductor channel region, performing plasma treatment on an exposed region of the two-dimensional semiconductor channel region to form an oxide layer, preparing a gate dielectric layer, and preparing a gate electrode on the surface of the gate dielectric layer. In the invention, the seed crystal layer is obtained by directly carrying out plasma treatment on the two-dimensional semiconductor, the interlayer coupling and the good interlayer interface of the two-dimensional material are utilized, the defect between the seed crystal layer and the two-dimensional semiconductor channel is effectively reduced, the seed crystal layer is used for assisting the growth of the gate dielectric layer, the high-quality gate dielectric layer is obtained, and the finally prepared top gate field effect transistor has good electrical properties such as low gate leakage current, small hysteresis and the like, reduces the power consumption, can adapt to advanced processes, and has wide application prospect in the manufacture of large-scale integrated circuits.

Inventors

  • BAO WENZHONG

Assignees

  • 原集微科技(上海)有限公司

Dates

Publication Date
20260512
Application Date
20260123

Claims (10)

  1. 1. The preparation method of the two-dimensional semiconductor top gate field effect transistor is characterized by comprising the following steps of: s1, preparing a source electrode and a drain electrode on the surface of a two-dimensional semiconductor material; S2, defining a two-dimensional semiconductor channel region by an etching process; S3, carrying out plasma treatment on the surface of the exposed area of the two-dimensional semiconductor channel area by oxygen so as to oxidize the surface of the two-dimensional semiconductor channel area to form an oxide layer to be used as a seed crystal layer for the growth of the gate dielectric layer; S4, preparing a gate dielectric layer; s5, preparing a grid electrode on the surface of the grid dielectric layer.
  2. 2. The method of manufacturing according to claim 1, wherein in step S1, a metal deposition process is used to manufacture the source electrode and the drain electrode; the number of layers of the two-dimensional semiconductor material is at least two.
  3. 3. The method of claim 2, wherein the source and drain electrodes are made of one of gold, platinum, palladium, ruthenium, antimony, bismuth, aluminum, indium, nickel, or titanium.
  4. 4. The method of manufacturing according to claim 1, wherein the etching process in step S2 is a dry etching process for removing the two-dimensional semiconductor material outside the two-dimensional semiconductor channel.
  5. 5. The method of claim 1, wherein in step S3, the plasma treatment is performed by capacitive plasma etching or inductively coupled plasma etching, and the oxide layer is formed to have a thickness of 1-3nm.
  6. 6. The method of claim 1, wherein the gate dielectric layer preparation process in step S4 is one of an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process; the gate dielectric layer covers the oxide layer, the source electrode and the drain electrode.
  7. 7. The method of claim 6 wherein the gate dielectric layer is made of one of tantalum oxide, yttrium oxide, zirconium oxide, hafnium oxide, aluminum oxide, or aluminum nitride.
  8. 8. The method of claim 1, wherein the gate electrode manufacturing process in step S5 is a metal deposition process.
  9. 9. The method of claim 8, wherein the gate electrode is made of one of gold, platinum, palladium, ruthenium, antimony, bismuth, aluminum, indium, nickel, or titanium.
  10. 10. A two-dimensional semiconductor top-gate field effect transistor prepared by the method of preparing a two-dimensional semiconductor top-gate field effect transistor as claimed in any one of claims 1 to 9.

Description

Two-dimensional semiconductor top gate field effect transistor and preparation method thereof Technical Field The invention relates to the technical field of semiconductor device preparation, in particular to a two-dimensional semiconductor top gate field effect transistor and a preparation method thereof. Background The field effect transistor with the top gate structure prepared by the two-dimensional semiconductor material is beneficial to the design of complex integrated circuits. Deposition of a high-k dielectric layer (using a dielectric material having a dielectric constant greater than SiO 2) is necessary for independent gate control and practical device operation from the transistor structural design perspective. However, forming a uniform and high quality dielectric layer on most two-dimensional semiconductor material surfaces is quite difficult because of the lack of dangling bonds for adsorption during oxide deposition on the two-dimensional semiconductor material surfaces during Atomic Layer Deposition (ALD), which limits its practical application in large scale circuits. To solve this problem, the insertion of a Seed Layer (SL) as an auxiliary layer for the growth of the gate dielectric has been studied as a method for two-dimensional semiconductor field effect transistors, as it provides a possible solution for post-gate processing techniques. The formation of a seed layer often involves direct deposition of metal or oxide, which can result in a number of defects in the interfacial contact between the two-dimensional semiconductor material channel and the seed layer, which often is reflected in hysteresis and bias temperature stability in subsequent transistor testing, severely affecting the performance and stability of the two-dimensional semiconductor transistor. Disclosure of Invention The invention aims to provide a two-dimensional semiconductor top gate field effect transistor and a preparation method thereof, wherein a seed crystal layer is prepared by adopting a mode of autoxidation of the surface of a two-dimensional semiconductor channel region in the preparation method so as to solve the problem that a large number of defects exist between a two-dimensional semiconductor channel and the seed crystal layer. In order to solve the above technical problem, a first aspect of the present invention provides a method for manufacturing a two-dimensional semiconductor top gate field effect transistor, including: s1, preparing a source electrode and a drain electrode on the surface of a two-dimensional semiconductor material; S2, defining a two-dimensional semiconductor channel region by an etching process; S3, carrying out plasma treatment on the surface of the exposed area of the two-dimensional semiconductor channel area by oxygen so as to oxidize the surface of the two-dimensional semiconductor channel area to form an oxide layer to be used as a seed crystal layer for the growth of the gate dielectric layer; S4, preparing a gate dielectric layer; s5, preparing a grid electrode on the surface of the grid dielectric layer. Preferably, in step S1, a metal deposition process is used to prepare a source electrode and a drain electrode; the number of layers of the two-dimensional semiconductor material is at least two. Preferably, the source electrode and the drain electrode are made of one of gold, platinum, palladium, ruthenium, antimony, bismuth, aluminum, indium, nickel or titanium. Preferably, the etching process in step S2 is a dry etching process for removing the two-dimensional semiconductor material outside the two-dimensional semiconductor channel. Preferably, in step S3, the plasma treatment is performed by capacitive plasma etching or inductively coupled plasma etching, and the oxide layer is formed to have a thickness of 1-3nm. Preferably, the gate dielectric layer preparation process in step S4 is one of an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process; the gate dielectric layer covers the oxide layer, the source electrode and the drain electrode. Preferably, the gate dielectric layer is made of one of tantalum oxide, yttrium oxide, zirconium oxide, hafnium oxide, aluminum oxide or aluminum nitride. Preferably, the gate preparation process in step S5 is a metal deposition process. Preferably, the material of the gate is selected from one of gold, platinum, palladium, ruthenium, antimony, bismuth, aluminum, indium, nickel or titanium. In order to solve the technical problem, a second aspect of the present invention is to provide a two-dimensional semiconductor top gate field effect transistor prepared by the preparation method of the two-dimensional semiconductor top gate field effect transistor. The preparation method of the two-dimensional semiconductor top gate field effect transistor provided by the invention has the advantages that the seed crystal layer is an oxide layer obtained by directly carrying out plasma trea