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CN-122028455-A - Method for manufacturing super junction SGT MOSFET

CN122028455ACN 122028455 ACN122028455 ACN 122028455ACN-122028455-A

Abstract

The invention provides a manufacturing method of a super junction SGT MOSFET, which comprises the steps of providing a substrate, forming an epitaxial layer, doping impurities of a first conductivity type and a second conductivity type in the epitaxial layer at the same time, etching a groove, thermally growing a dielectric layer on the inner wall of the groove, enabling the impurities of the first type to gather at an interface by utilizing the difference of segregation coefficients of the two impurities in the dielectric layer and the epitaxial layer, enabling the impurities of the second type to be consumed, enabling the conductivity type of the area adjacent to the inner wall of the groove to be inverted, forming a first type doping area surrounding the groove, and forming a super junction structure, and then manufacturing a shielding gate, a control gate and a source drain. The invention naturally forms the superjunction by utilizing the impurity segregation effect, does not need high-energy injection or multiple epitaxy, is compatible with the prior SGT process, obviously reduces the cost and improves the performance of devices.

Inventors

  • SHI KUAN
  • CHEN SITONG
  • WANG YU
  • CHEN XUETING
  • PAN JIA
  • YANG JIYE

Assignees

  • 华虹半导体制造(无锡)有限公司
  • 华虹半导体(无锡)有限公司
  • 上海华虹宏力半导体制造有限公司

Dates

Publication Date
20260512
Application Date
20260129

Claims (20)

  1. 1. A method for fabricating a super junction SGT MOSFET, comprising: Providing a substrate, forming an epitaxial layer on the substrate, wherein the epitaxial layer is doped with first conductive type impurity ions and second conductive type impurity ions at the same time, and the concentration of the second conductive type impurity ions is higher than that of the first conductive type impurity ions, so that the whole epitaxial layer presents the polarity of the second conductive type; Step two, forming a groove on the epitaxial layer, wherein the groove extends along the thickness direction of the epitaxial layer; And thirdly, forming a dielectric layer on the inner wall of the groove, utilizing the difference of segregation coefficients of the first conductive type impurity ions and the second conductive type impurity ions in the dielectric layer and the epitaxial layer material, enabling the first conductive type impurity ions to gather at one side of the epitaxial layer at the interface of the dielectric layer and the epitaxial layer, enabling the second conductive type impurity ions to enter the dielectric layer and be consumed, enabling a region adjacent to the inner wall of the groove to generate conductive type inversion, forming a first conductive type doped region surrounding the groove, enabling the epitaxial layer to be kept as a second conductive type doped region in a region far away from the groove, and enabling the first conductive type doped region and the second conductive type doped region to form a super junction structure.
  2. 2. The method of claim 1, wherein in step one, the epitaxial layer material is silicon.
  3. 3. The method of manufacturing a super junction SGT MOSFET of claim 1, wherein in step one, said first conductivity type impurity ions are N-type impurities.
  4. 4. The method of manufacturing a super junction SGT MOSFET of claim 3, wherein in step one, said impurity ions of said first conductivity type include arsenic or phosphorous.
  5. 5. The method of manufacturing a super junction SGT MOSFET of claim 1, wherein in step one, said impurity ions of the second conductivity type are P-type impurities.
  6. 6. The method of manufacturing a super junction SGT MOSFET of claim 5, wherein in step one, said impurity ions of the second conductivity type include boron.
  7. 7. The method of claim 1, wherein in the first step, the epitaxial layer has a multi-layer graded concentration structure or a graded concentration structure.
  8. 8. The method of claim 1, wherein in the second step, the aspect ratio of the trench is greater than 5.
  9. 9. The method of manufacturing a super junction SGT MOSFET of claim 1 wherein in step three, the process of forming the dielectric layer is a thermal oxidation process.
  10. 10. The method of manufacturing a super junction SGT MOSFET of claim 1 wherein in step three, the dielectric layer is a silicon oxide layer.
  11. 11. The method of manufacturing a super junction SGT MOSFET of claim 10, wherein in step three, the first conductivity type impurity ions have a solubility in silicon greater than a solubility in silicon oxide.
  12. 12. The method of manufacturing a super junction SGT MOSFET of claim 10, wherein in step three, the second conductivity type impurity ions have a solubility in silicon oxide greater than a solubility in silicon.
  13. 13. The method of claim 1, wherein in the third step, the dielectric layer has a thickness of 5000A to 10000A.
  14. 14. The method of manufacturing a super junction SGT MOSFET of claim 1, wherein in step three, the concentration of impurity ions of the first conductivity type is raised to 2.0 times to 3.0 times the initial concentration at the interface of the dielectric layer and the epitaxial layer.
  15. 15. The method of manufacturing a super junction SGT MOSFET of claim 1, wherein in step three, the concentration of impurity ions of the second conductivity type is reduced to 0.4 times to 0.8 times the initial concentration at the interface of the dielectric layer and the epitaxial layer.
  16. 16. The method of manufacturing a super junction SGT MOSFET of claim 1, further comprising a fourth step of filling a shield gate conductive material in the trench formed with the dielectric layer after the third step to form a shield gate.
  17. 17. The method of claim 16, wherein in step four, the shielding gate conductive material is polysilicon.
  18. 18. The method of manufacturing a super junction SGT MOSFET of claim 16, wherein in step four, forming a shield gate comprises etching back the shield gate conductive material by a dry etching process to planarize a top surface thereof.
  19. 19. The method of manufacturing a super junction SGT MOSFET of claim 16, further comprising removing a portion of the dielectric layer and a portion of the shielding gate conductive material after step four, forming a gate dielectric layer over the trench, and filling a control gate conductive material over the gate dielectric layer to form a control gate.
  20. 20. The method of claim 19, wherein in step five, the control gate conductive material is polysilicon.

Description

Method for manufacturing super junction SGT MOSFET Technical Field The invention relates to the field of integrated circuit manufacturing, in particular to a manufacturing method of a super junction SGT MOSFET. Background Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are the core components of power semiconductor devices. Among them, the Shielded Gate Trench (SGT) MOSFET has been widely used in power management and medium-low voltage applications because it has integrated a shielding electrode in the lower portion of the trench, which can significantly reduce the gate-drain capacitance (Cgd), thereby reducing switching losses and improving device performance. On the other hand, the Super Junction (SJ) technology breaks the limit relation between the specific on-resistance and the breakdown voltage of the traditional silicon device by introducing an alternately arranged P-type region and N-type region structure in the drift region of the device and utilizing the charge balance principle. However, because the medium and low voltage MOSFET products are extremely cost sensitive, conventional superjunction shielded gate SGT fabrication processes face significant challenges. The existing super junction manufacturing process, such as multiple epitaxial growth and multiple ion implantation or deep groove high-energy ion implantation, has the defects of complicated process steps, long production period and extremely high equipment requirements, and causes high manufacturing cost. In addition, the epitaxial layer of the conventional SGT MOSFET is relatively thin, if super-junction is manufactured by adopting non-epitaxial modes such as oblique injection of the side wall of the trench, the difficulty in accurate doping control in the narrow trench is great, and the doping is not uniform easily caused by shadow effect. Therefore, there is a need in the industry for a low cost, well compatible method of fabricating super junction SGT MOSFETs. Disclosure of Invention The technical problem to be solved by the invention is that the existing super-junction MOSFET manufacturing process generally adopts methods of multiple epitaxial growth and multiple ion implantation or deep groove high-energy ion implantation and the like, the methods are complex in process, expensive in equipment and long in period and are difficult to apply to medium-low voltage products sensitive to cost, while the conventional SGT MOSFET is relatively mature in process, but the super-junction structure is difficult to introduce on the premise of not adding expensive equipment so as to break the resistance-withstand voltage limit of the silicon material. In view of the above, the invention provides a manufacturing method which utilizes the impurity segregation effect to naturally form a super junction structure, has low cost and is compatible with the existing SGT technology. The invention provides a manufacturing method of a super junction SGT MOSFET, which comprises the following steps: Providing a substrate, forming an epitaxial layer on the substrate, wherein the epitaxial layer is doped with first conductive type impurity ions and second conductive type impurity ions at the same time, and the concentration of the second conductive type impurity ions is higher than that of the first conductive type impurity ions, so that the whole epitaxial layer presents the polarity of the second conductive type; Step two, forming a groove on the epitaxial layer, wherein the groove extends along the thickness direction of the epitaxial layer; And thirdly, forming a dielectric layer on the inner wall of the groove, utilizing the difference of segregation coefficients of the first conductive type impurity ions and the second conductive type impurity ions in the dielectric layer and the epitaxial layer material, enabling the first conductive type impurity ions to gather at one side of the epitaxial layer at the interface of the dielectric layer and the epitaxial layer, enabling the second conductive type impurity ions to enter the dielectric layer and be consumed, enabling a region adjacent to the inner wall of the groove to generate conductive type inversion, forming a first conductive type doped region surrounding the groove, enabling the epitaxial layer to be kept as a second conductive type doped region in a region far away from the groove, and enabling the first conductive type doped region and the second conductive type doped region to form a super junction structure. Preferably, in the first step, the epitaxial layer material is silicon. Preferably, in the first step, the first conductivity type impurity ion is an N-type impurity. Preferably, in the first step, the first conductive type impurity ions include arsenic or phosphorus. Preferably, in the first step, the second conductivity type impurity ions are P-type impurities. Preferably, in the first step, the second conductivity type impurity ions include boron. Preferably, in the first step, t