CN-122028456-A - Preparation method of PMOS device

CN122028456ACN 122028456 ACN122028456 ACN 122028456ACN-122028456-A

Abstract

The invention provides two preparation methods of PMOS devices, wherein in the process of P-type ion implantation of source electrode contact and drain electrode contact or P-type ion implantation of source electrode and drain electrode, a hard mask layer on a gate polysilicon layer is utilized to block the P-type ion from being implanted into the gate polysilicon layer, so that the problems that P-type ions in the gate polysilicon layer penetrate through a gate dielectric layer below the gate polysilicon layer and enter a silicon substrate channel below the gate polysilicon layer to cause drift of electrical performance of the PMOS devices, degradation of the integrity of the gate dielectric layer and reduction of reliability are solved, and other defects are not additionally introduced in the method, so that the process is simple and easy to realize.

Inventors

WANG SHAOZHAO

Assignees

芯恩（青岛）集成电路有限公司

Dates

Publication Date: 20260512
Application Date: 20260212

Claims (11)

1. The preparation method of the PMOS device is characterized by comprising the following steps of: S1, providing a silicon substrate, wherein a grid structure of a semiconductor device and a hard mask layer covering the grid structure are formed on the silicon substrate, and the grid structure comprises a grid dielectric layer and a grid polysilicon layer; s2, forming first side walls on the two side walls of the grid structure and the hard mask layer; s3, ion implantation is carried out to form an LDD region and a halo region; S4, forming a first sacrificial dielectric layer and a second sacrificial dielectric layer which are sequentially stacked on the side wall of the first side wall; s5, etching the silicon substrate on two sides of the second sacrificial dielectric layer by taking the second sacrificial dielectric layer as a mask to form a source drain groove; S6, forming a SiGe epitaxial layer and a silicon cap layer which at least fill the source drain electrode groove by adopting a selective epitaxial process; S7, performing P-type ion implantation on the silicon cap layer based on the protection of the hard mask layer on the gate polysilicon layer to form a source electrode contact and a drain electrode contact; S8, removing the first sacrificial dielectric layer, the second sacrificial dielectric layer, the hard mask layer and the first side walls of the two side walls of the hard mask layer, and only keeping the first side walls of the two side walls of the grid structure; S9, forming second side walls on two side walls of the first side wall.
2. The method of manufacturing a PMOS device according to claim 1, wherein the method of forming the gate structure and the hard mask layer overlying the gate structure in step S1 comprises: the method comprises the steps of providing a silicon substrate, wherein the silicon substrate comprises a P-type substrate layer positioned on a lower layer and an N-well layer positioned on an upper layer; sequentially forming the gate dielectric layer, the gate polysilicon layer and the silicon oxide adhesion layer on the surface of the silicon substrate; Forming the hard mask layer on the surface of the silicon oxide adhesion layer, and patterning to obtain the patterned hard mask layer; and etching the silicon oxide adhesion layer, the gate polysilicon layer and the gate dielectric layer in sequence based on the patterned hard mask layer.
3. The method for manufacturing the PMOS device according to claim 2, wherein the gate dielectric layer is a SiON layer or a SiO 2 layer, the silicon oxide adhesion layer is formed by a thermal oxidation process, the thickness of the silicon oxide adhesion layer is 10-50A, ion implantation is performed on the gate polysilicon layer after the silicon oxide adhesion layer is formed and before the hard mask layer is formed so as to preset and adjust the work function of the gate structure, the hard mask layer is a SiON layer or a SiN layer, and the thickness of the hard mask layer is 300-500A.
4. The method of manufacturing a PMOS device of claim 1, wherein in step S2, the first sidewall comprises a silicon oxide layer on both sidewall surfaces of the gate structure and the hard mask layer, and a low-k dielectric layer on the surface of the silicon oxide layer.
5. The method of manufacturing a PMOS device according to claim 1, wherein in step S5, the first sacrificial dielectric layer is a SiO 2 layer and the second sacrificial dielectric layer is a SiN layer.
6. The method of manufacturing a PMOS device according to claim 1, wherein in step S8, a wet etching process is used to remove the first sacrificial dielectric layer, the second sacrificial dielectric layer, the hard mask layer and the first sidewall of the two sidewalls of the hard mask layer.
7. The method of manufacturing a PMOS device of claim 1, wherein in step S9, the second sidewall is formed between the first sidewall and the silicon cap layer.
8. The method of claim 1, further comprising forming a salicide layer on the source contact, the drain contact, and the gate structure surface after step S9, and forming an ILD dielectric layer and a conductive contact hole after forming the salicide layer.
9. The preparation method of the PMOS device is characterized by comprising the following steps of: S1, providing a silicon substrate, wherein a grid structure of a semiconductor device and a hard mask layer covering the grid structure are formed on the silicon substrate, and the grid structure comprises a grid dielectric layer and a grid polysilicon layer; s2, forming first side walls on the two side walls of the grid structure and the hard mask layer; s3, ion implantation is carried out to form an LDD region and a halo region; S4, forming a first sacrificial dielectric layer and a second sacrificial dielectric layer which are sequentially stacked on the side wall of the first side wall; S5, performing P-type ion implantation on the surfaces of the silicon substrates at two sides of the second sacrificial dielectric layer based on the protection of the hard mask layer on the gate polysilicon layer so as to form a source electrode and a drain electrode; S6, removing the first sacrificial dielectric layer, the second sacrificial dielectric layer, the hard mask layer and the first side walls of the two side walls of the hard mask layer, and only keeping the first side walls of the two side walls of the grid structure; s7, forming second side walls on two side walls of the first side wall.
10. The method of manufacturing a PMOS device of claim 9, further comprising forming a salicide layer over the source, drain and gate structures, and forming an ILD dielectric layer and a conductive contact hole after forming the salicide layer after step S7.
11. The method of manufacturing a PMOS device of claim 9, wherein in step S7, the second sidewall is formed between the first sidewall and the source or the drain.

Description

Preparation method of PMOS device Technical Field The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a PMOS device. Background In the integrated process of the planar gate PMOS device, source/drain ion implantation is generally performed after the side wall is etched, at this time, the top of the polysilicon gate layer is completely exposed, and in order to reduce the source/drain contact resistance, a higher boron (B) ion implantation concentration is generally required, which leads to a higher B ion doping concentration in the polysilicon gate, and after annealing, the B ions in the polysilicon gate pass through an ultrathin gate dielectric layer below the polysilicon gate and enter a substrate channel below the polysilicon gate, so that the electrical performance of the PMOS device drifts, the integrity of the gate dielectric layer is degraded, and the reliability is reduced. For this reason, in some examples, a silicon oxynitride doped gate dielectric layer is used, and nitrogen atoms are used to reduce diffusion of B, but the silicon oxynitride doped gate dielectric layer is generally thinner, such as about 28nm node 20 a, and has limited blocking capability, for example, BF 2 is used to replace B ions, BF 2 ions have larger mass and are not easy to diffuse, but F ions are easy to precipitate, and other problems are caused, for example, by optimizing an annealing process, such as an RTP process, and a rapid thermal annealing process is used to complete activation and lattice repair before B penetration (B duration), but the process window is low and difficult to control accurately. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a PMOS device, which is used to solve the problems of drift in electrical performance and degradation in reliability caused by penetration of a PMOS device B in the process of manufacturing the PMOS device in the prior art, wherein the improvement method adopted has limited diffusion blocking capability to B, and some problems of B penetration but other defects are introduced, and some problems of B penetration but low process window and high process difficulty are solved. To achieve the above and other related objects, the present invention provides a method for manufacturing a PMOS device, including the steps of: S1, providing a silicon substrate, wherein a grid structure of a semiconductor device and a hard mask layer covering the grid structure are formed on the silicon substrate, and the grid structure comprises a grid dielectric layer and a grid polysilicon layer; s2, forming first side walls on the two side walls of the grid structure and the hard mask layer; s3, ion implantation is carried out to form an LDD region and a halo region; S4, forming a first sacrificial dielectric layer and a second sacrificial dielectric layer which are sequentially stacked on the side wall of the first side wall; s5, etching the silicon substrate on two sides of the second sacrificial dielectric layer by taking the second sacrificial dielectric layer as a mask to form a source drain groove; S6, forming a SiGe epitaxial layer and a silicon cap layer which at least fill the source drain electrode groove by adopting a selective epitaxial process; S7, performing P-type ion implantation on the silicon cap layer based on the protection of the hard mask layer on the gate polysilicon layer to form a source electrode contact and a drain electrode contact; S8, removing the first sacrificial dielectric layer, the second sacrificial dielectric layer, the hard mask layer and the first side walls of the two side walls of the hard mask layer, and only keeping the first side walls of the two side walls of the grid structure; S9, forming second side walls on two side walls of the first side wall. Optionally, the method for forming the gate structure and the hard mask layer covering the gate structure in step S1 includes: the method comprises the steps of providing a silicon substrate, wherein the silicon substrate comprises a P-type substrate layer positioned on a lower layer and an N-well layer positioned on an upper layer; sequentially forming the gate dielectric layer, the gate polysilicon layer and the silicon oxide adhesion layer on the surface of the silicon substrate; Forming the hard mask layer on the surface of the silicon oxide adhesion layer, and patterning to obtain the patterned hard mask layer; and etching the silicon oxide adhesion layer, the gate polysilicon layer and the gate dielectric layer in sequence based on the patterned hard mask layer. Further, the gate dielectric layer is a SiON layer or a SiO 2 layer, the silicon oxide adhesion layer is formed by adopting a thermal oxidation process, the thickness of the silicon oxide adhesion layer is 10-50A, ion implantation is carried out