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CN-122028460-A - Multi-channel transistor capable of reducing turn-off difficulty and preparation method thereof

CN122028460ACN 122028460 ACN122028460 ACN 122028460ACN-122028460-A

Abstract

The disclosure provides a multichannel transistor capable of reducing turn-off difficulty and a preparation method thereof, and belongs to the field of power electronics. The multi-channel transistor comprises an epitaxial layer, a p-type layer, a gate electrode, a source electrode and a drain electrode, wherein the epitaxial layer comprises at least two layers of stacked heterojunctions, a first groove extending to the bottommost part of the heterojunctions is formed in the top surface of the epitaxial layer, the p-type layer is located on the side wall and the bottom of the first groove, the gate electrode is located on the surface of the p-type layer and at least located in the first groove, the source electrode and the drain electrode are located on the epitaxial layer and are distributed on two sides of the gate electrode at intervals, and the source electrode and the drain electrode are electrically connected with the heterojunctions. The embodiment of the disclosure can solve the problem that the bottom channel of the multi-channel transistor is difficult to control to be turned off, and reduce the control difficulty of the multi-channel transistor.

Inventors

  • YANG YING
  • WANG RUI
  • YANG TING

Assignees

  • 京东方华灿光电(广东)有限公司

Dates

Publication Date
20260512
Application Date
20251217

Claims (10)

  1. 1. A multi-channel transistor, characterized in that the multi-channel transistor comprises an epitaxial layer (10), a p-type layer (20), a gate electrode (31), a source electrode (32) and a drain electrode (33); The epitaxial layer (10) comprises at least two layers of stacked heterojunctions (11), a first groove (101) extending to the bottommost heterojunctions (11) is formed in the top surface of the epitaxial layer (10), the p-type layer (20) is located on the side wall and the groove bottom of the first groove (101), and the gate electrode (31) is located on the surface of the p-type layer (20) and at least located in the first groove (101); the source electrode (32) and the drain electrode (33) are located on the epitaxial layer (10) and are arranged on two sides of the gate electrode (31) at intervals, and the source electrode (32) and the drain electrode (33) are electrically connected with the heterojunction (11).
  2. 2. The multi-channel transistor according to claim 1, wherein a top surface of the epitaxial layer (10) is provided with a plurality of the first grooves (101), the plurality of the first grooves (101) are arranged at intervals along a first direction (1 a), and the gate electrode (31) is further located on the top surface of the epitaxial layer (10) and extends into each of the first grooves (101); The source electrode (32), the gate electrode (31) and the drain electrode (33) are arranged at intervals along a second direction (1 b), and the first direction (1 a) is perpendicular to the second direction (1 b).
  3. 3. The multi-channel transistor according to claim 2, characterized in that the orthographic projection of each first recess (101) on the bottom surface of the epitaxial layer (10) is located within the orthographic projection of the gate electrode (31) on the bottom surface of the epitaxial layer (10).
  4. 4. A multi-channel transistor according to any of claims 1 to 3, characterized in that the hole concentration of the p-type layer (20) is 1 x 10 17 cm -3 to 5 x 10 17 cm -3 .
  5. 5. The multi-channel transistor according to claim 4, wherein the thickness of the p-type layer (20) is 70nm to 100nm.
  6. 6. The multi-channel transistor of claim 4, wherein the p-type layer (20) comprises a p-type GaN layer and the doped material of the p-type GaN layer comprises Mg, zn, and Ga.
  7. 7. A multi-channel transistor according to any of claims 1 to 3, characterized in that the multi-channel transistor further comprises a dielectric layer (41), the dielectric layer (41) being located on the top surface of the epitaxial layer (10), the surface of the dielectric layer (41) remote from the epitaxial layer (10) having a stepped groove (410), the orthographic projection of the first groove (101) on the bottom surface of the epitaxial layer (10) being located within the orthographic projection of the stepped groove (410) on the bottom surface of the epitaxial layer (10); the stepped groove (410) comprises at least two sections of coaxially communicated stepped holes, and the aperture of each stepped hole is positively correlated with the distance from the stepped hole to the epitaxial layer (10).
  8. 8. A multi-channel transistor according to any of claims 1 to 3, characterized in that the source electrode (32), the drain electrode (33) and the gate electrode (31) each comprise at least one of a Ti layer, an Al layer and a TiN layer.
  9. 9. A method of fabricating a multi-channel transistor, the method comprising: forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises at least two layers of laminated heterojunctions; Forming a first groove on the top surface of the epitaxial layer, wherein the first groove extends to the bottommost heterojunction; Forming a p-type layer on the side wall and the bottom of the first groove; forming a gate electrode on the surface of the p-type layer, wherein the gate electrode is at least positioned in the first groove; And forming a source electrode and a drain electrode on the epitaxial layer, wherein the source electrode and the drain electrode are arranged on two sides of the gate electrode, and the source electrode and the drain electrode are electrically connected with each heterojunction.
  10. 10. The method of claim 9, wherein forming a first recess in a top surface of the epitaxial layer comprises: The method comprises the steps of forming a plurality of first grooves on the top surface of an epitaxial layer, arranging the first grooves at intervals along a first direction, arranging a gate electrode on the top surface of the epitaxial layer and extending into each first groove, arranging a source electrode, a gate electrode and a drain electrode at intervals along a second direction, and enabling the first direction to be perpendicular to the second direction.

Description

Multi-channel transistor capable of reducing turn-off difficulty and preparation method thereof Technical Field The disclosure relates to the field of power electronics, and in particular relates to a multichannel transistor capable of reducing turn-off difficulty and a preparation method thereof. Background Gallium nitride as a third generation wide bandgap semiconductor material exhibits significant advantages in high frequency, high power electronic devices due to its excellent physical and electrical properties, such as high electron mobility, high thermal stability, and wide bandgap. As an extension of the structure of a high electron mobility transistor, a multi-channel transistor has received attention in recent years. In the related art, a multi-channel transistor includes a multi-layered stacked AlGaN/GaN heterojunction, and a plurality of parallel two-dimensional electron gas (2 DEG) channels are introduced by stacking a plurality of heterojunctions, so that carrier density per unit area can be increased, thereby enhancing current driving capability of the transistor and reducing on-resistance. Because the vertical distance between the grid and each channel is different, the electric field control capability of the grid to different channels is attenuated from top to bottom. Therefore, the overall threshold voltage of the transistor is determined by all channels, and in order to ensure that the transistor is completely turned off, the gate voltage must be low enough to deplete the bottom channel that is most difficult to control, which results in that the threshold voltage of the transistor usually exhibits a significant negative shift, and a negative gate voltage needs to be applied to be large enough to achieve the turn-off, which increases the difficulty in circuit design and power consumption control. Disclosure of Invention The embodiment of the disclosure provides a multi-channel transistor capable of reducing turn-off difficulty and a preparation method thereof, which can solve the problem that a bottom channel in the multi-channel transistor is difficult to control turn-off and reduce the control difficulty of the multi-channel transistor. The technical scheme is as follows: In one aspect, the embodiment of the disclosure provides a multi-channel transistor, which comprises an epitaxial layer, a p-type layer, a gate electrode, a source electrode and a drain electrode, wherein the epitaxial layer comprises at least two layers of stacked heterojunctions, a first groove extending to the bottommost part of the heterojunctions is formed in the top surface of the epitaxial layer, the p-type layer is located on the side wall and the bottom of the first groove, the gate electrode is located on the surface of the p-type layer and at least located in the first groove, the source electrode and the drain electrode are located on the epitaxial layer and are distributed on two sides of the gate electrode at intervals, and the source electrode and the drain electrode are electrically connected with each heterojunction. In one implementation manner of the present disclosure, the top surface of the epitaxial layer is provided with a plurality of first grooves, the plurality of first grooves are arranged at intervals along a first direction, the gate electrode is further located on the top surface of the epitaxial layer and extends into each first groove, the source electrode, the gate electrode and the drain electrode are arranged at intervals along a second direction, and the first direction is perpendicular to the second direction. In another implementation of the disclosure, an orthographic projection of each of the first grooves on the bottom surface of the epitaxial layer is located within an orthographic projection of the gate electrode on the bottom surface of the epitaxial layer. In another implementation of the present disclosure, the hole concentration of the p-type layer is 1×10 17cm-3 to 5×10 17cm-3. In another implementation of the present disclosure, the p-type layer has a thickness of 70nm to 100nm. In another implementation of the present disclosure, the p-type layer includes a p-type GaN layer, and the doping material of the p-type GaN layer includes Mg, zn, and Ga. In another implementation manner of the disclosure, the multi-channel transistor further comprises a dielectric layer, the dielectric layer is located on the top surface of the epitaxial layer, a stepped groove is formed in the surface, far away from the epitaxial layer, of the dielectric layer, orthographic projection of the first groove on the bottom surface of the epitaxial layer is located in orthographic projection of the stepped groove on the bottom surface of the epitaxial layer, the stepped groove comprises at least two sections of coaxially communicated stepped holes, and the aperture of each stepped hole is positively correlated with the distance from the stepped hole to the epitaxial layer. In another implementation