CN-122028461-A - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Abstract

The invention provides a semiconductor device which comprises a bottom layer structure, a first potential barrier structure and a second potential barrier structure, a grid structure, a source electrode structure and a drain electrode structure, wherein the first potential barrier structure and the second potential barrier structure are arranged on the upper surface of the bottom layer structure, the first potential barrier structure and the second potential barrier structure are arranged side by side and jointly cover the upper surface of the bottom layer structure, the grid structure is arranged on the upper surface of the first potential barrier structure, the source electrode structure and the drain electrode structure are respectively arranged on two opposite sides of the grid structure, the source electrode structure and the drain electrode structure are arranged at intervals with the grid structure, and the polarization effect intensity between the second potential barrier structure and the channel layer is larger than that between the first potential barrier structure and the channel layer. The device comprises a barrier structure with two parts, and the concentration of carriers in a channel can be regulated and controlled in a segmented mode, so that the electric field at the corners of a drain electrode and a source electrode and the on-resistance of the device are reduced. And the threshold voltage of the device is ensured and the on-resistance is not influenced by common adjustment of the barrier layer and the stress modulation layer.

Inventors

• ZHAO QIYUE
• ZHANG LI

Assignees

• 矽力杰半导体技术(杭州)有限公司

Dates

Publication Date

20260512

Application Date

20260116

Claims (20)

1. 1. A semiconductor device, the device comprising: A substructure comprising at least a base layer and a channel layer over the base layer, The first barrier structure and the second barrier structure are arranged side by side and jointly cover the upper surface of the bottom structure, and two-dimensional electron gas is formed between the channel layer and the first barrier structure and between the channel layer and the second barrier structure; A gate structure located on an upper surface of the first barrier structure; The source electrode structure and the drain electrode structure are respectively positioned on two opposite sides of the grid electrode structure, and the source electrode structure and the drain electrode structure are arranged at intervals with the grid electrode structure; wherein the polarization effect intensity between the second barrier structure and the channel layer is greater than the polarization effect intensity between the first barrier structure and the channel layer.
2. 2. The semiconductor device of claim 1, wherein the gate structure comprises a P-type gate overlying an upper surface of the first barrier structure and a gate electrode overlying an upper surface of the P-type gate.
3. 3. The semiconductor device of claim 1, wherein the gate structure comprises a gate dielectric layer overlying the upper surface of the first barrier structure and a gate electrode overlying the upper surface of the gate dielectric layer.
4. 4. The semiconductor device of claim 1, wherein the gate structure comprises a gate electrode overlying an upper surface of the first barrier structure.
5. 5. The semiconductor device of claim 2, 3 or 4, wherein the source structure is an ohmic contact source structure, the drain structure is an ohmic contact drain structure, and the source structure and the drain structure lower surface extend to the channel layer.
6. 6. The semiconductor device of claim 5, wherein the first barrier structure comprises a first barrier layer having a bandgap width that is greater than a bandgap width of the channel layer.
7. 7. The semiconductor device of claim 6, wherein the material of the first barrier layer comprises a ternary group III nitride.
8. 8. The semiconductor device of claim 6, wherein the first barrier structure further comprises a first stress modulation layer located between the channel layer and the first barrier layer, wherein a band gap width of the first barrier layer is less than a band gap width of the first stress modulation layer.
9. 9. The semiconductor device of claim 8, wherein the material of the first stress modulation layer comprises a binary group III nitride and the material of the first barrier layer comprises a ternary group III nitride.
10. 10. The semiconductor device of claim 6, wherein the second barrier structure comprises a second stress modulation layer on an upper surface of the channel layer and a second barrier layer on an upper surface of the second stress modulation layer, wherein a band gap width of the second barrier layer is greater than a band gap width of the channel layer but less than a band gap width of the second stress modulation layer.
11. 11. The semiconductor device of claim 10, wherein the material of the second stress modulation layer comprises a binary group III nitride and the material of the second barrier layer comprises a ternary group III nitride.
12. 12. The semiconductor device of claim 10, wherein the second barrier structure further comprises a third barrier layer on an upper surface of the second barrier layer, the third barrier layer for preventing oxidation of the second barrier layer.
13. 13. The semiconductor device of claim 12, wherein the material of the second stress modulation layer comprises a binary group III nitride, the material of the second barrier layer comprises a ternary group III nitride, the material of the third barrier layer comprises a binary group III nitride, and the band gap width of the second stress modulation layer is greater than the band gap width of the third barrier layer.
14. 14. The semiconductor device of claim 10, wherein the second barrier structure comprises a first portion on a first side of the first barrier structure and a second portion on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.
15. 15. The semiconductor device of claim 12, wherein the second barrier structure comprises a first portion on a first side of the first barrier structure and a second portion on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.
16. 16. The semiconductor device of claim 8, wherein the second barrier structure comprises a second stress modulation layer on an upper surface of the channel layer and a second barrier layer on an upper surface of the second stress modulation layer, wherein a band gap width of the second barrier layer is greater than a band gap width of the channel layer but less than a band gap width of the second stress modulation layer.
17. 17. The semiconductor device of claim 16, wherein the material of the second stress modulation layer comprises a binary group III nitride and the material of the second barrier layer comprises a ternary group III nitride.
18. 18. The semiconductor device of claim 16, wherein the second barrier structure further comprises a third barrier layer on an upper surface of the second barrier layer, the third barrier layer for preventing oxidation of the second barrier layer.
19. 19. The semiconductor device of claim 18, wherein the material of the second stress modulation layer comprises a binary group III nitride, the material of the second barrier layer comprises a ternary group III nitride, the material of the third barrier layer comprises a binary group III nitride, and the band gap width of the second stress modulation layer is greater than the band gap width of the third barrier layer.
20. 20. The semiconductor device of claim 16, wherein the second barrier structure comprises a first portion on a first side of the first barrier structure and a second portion on a second side of the first barrier structure, wherein the first side and the second side are opposite sides.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Technical Field The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a semiconductor device. Background The GaN high electron mobility transistor (High Electron Mobility Transistor, HEMT for short) has the advantages of wide band gap, high breakdown field strength, high electron mobility, high energy conversion efficiency and the like, and has great potential in high-frequency high-power electronic power application. However, the conventional GaN HEMT has a difficulty in independently controlling the carrier concentration under the gate (i.e. controlling the threshold voltage of the device) without affecting the carrier concentration of the access region (between the gate and the source and between the gate and the drain) due to the lack of effective ion doping and activation methods, which severely limits the flexibility of GaN device design. However, in order to raise the threshold voltage of the device, it is generally necessary to reduce the polarization intensity of the barrier layer and the channel layer of the device to reduce the concentration of channel carriers of the device, but this causes an increase in the on-resistance of the device. How to increase the threshold voltage of the device and reduce the on-resistance of the device is an urgent problem to be solved in the prior art. Disclosure of Invention In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a semiconductor device for solving the technical problem that the device in the prior art cannot achieve both of increasing the threshold voltage of the device and reducing the on-resistance of the device. In order to achieve the aim, the invention provides a semiconductor device, which comprises a bottom layer structure, a grid structure, a source electrode structure and a drain electrode structure, wherein the bottom layer structure at least comprises a substrate layer and a channel layer arranged above the substrate layer, the first barrier structure and the second barrier structure are arranged side by side and jointly cover the upper surface of the bottom layer structure, two-dimensional electron gas is formed between the channel layer and the first barrier structure and between the second barrier structure, the grid structure is arranged on the upper surface of the first barrier structure, the source electrode structure and the drain electrode structure are respectively arranged on two opposite sides of the grid structure and are arranged at intervals with the grid structure, and the polarization effect intensity between the second barrier structure and the channel layer is larger than that between the first barrier structure and the channel layer. In other embodiments, the gate structure includes a P-type gate overlying the upper surface of the first barrier structure and a gate electrode overlying the upper surface of the P-type gate. In other embodiments, the gate structure comprises a gate dielectric layer covering the upper surface of the first barrier structure and a gate electrode covering the upper surface of the gate dielectric layer. In other embodiments, the gate structure includes a gate electrode overlying an upper surface of the first barrier structure. In other embodiments, the source structure is an ohmic contact source structure, the drain structure is an ohmic contact drain structure, and the source structure and the drain structure lower surface extend to the channel layer. In other embodiments, the first barrier structure includes a first barrier layer having a bandgap width that is greater than a bandgap width of the channel layer. In other embodiments, the material of the first barrier layer includes ternary group III nitride. In other embodiments, the first barrier structure further comprises a first stress modulation layer located between the channel layer and the first barrier layer, wherein a bandgap width of the first barrier layer is less than a bandgap width of the first stress modulation layer. In other embodiments, the material of the first stress modulation layer includes binary group III nitride, and the material of the first barrier layer includes ternary group III nitride. In other embodiments, the second barrier structure includes a second stress modulation layer on the upper surface of the channel layer and a second barrier layer on the upper surface of the second stress modulation layer, wherein a band gap width of the second barrier layer is greater than a band gap width of the channel layer but less than a band gap width of the second stress modulation layer. In other embodiments, the material of the second stress modulation layer includes binary group III nitride, and the material of the second barrier layer includes ternary group III nitride. In other embodiments, the second barrier structure fu