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CN-122028463-A - Semiconductor device and radio frequency module

CN122028463ACN 122028463 ACN122028463 ACN 122028463ACN-122028463-A

Abstract

The invention relates to a semiconductor device and a radio frequency module. The through hole of the semiconductor device extends from the substrate to the direction of the semiconductor lamination to penetrate through the semiconductor lamination and expose the source electrode, the through hole comprises a first hole section which is positioned in the substrate and connected with the second surface, and a second hole section which spans between the substrate and the semiconductor lamination, one hole section of the second hole Duan Zidi extends to the semiconductor lamination and penetrates through the semiconductor lamination, the metal layer covers the second surface and extends to the side wall of the through hole and is contacted with the source electrode, and the thickness of the metal layer covering the side wall of the through hole is reduced from the second surface to the direction of the semiconductor lamination. The invention can effectively improve the comprehensive performance and reliability of the device.

Inventors

  • ZHONG JIEBIN
  • HUANG LONGQUAN
  • LIU SHENGHOU
  • SUN XIGUO
  • WANG XIAOYUAN

Assignees

  • 泉州市三安集成电路有限公司

Dates

Publication Date
20260512
Application Date
20251119

Claims (20)

  1. 1. A semiconductor device, comprising: A substrate having a first surface and a second surface opposite to each other; A semiconductor stack on the first surface, the semiconductor stack having one side and another side opposite to each other, the one side of the semiconductor stack being in contact with the first surface; a source electrode located on the other surface of the semiconductor stack; A through hole extending from the second surface to the substrate and the semiconductor lamination along the thickness direction of the substrate in sequence to penetrate through the semiconductor lamination and expose the source electrode; a metal layer covering the second surface and extending to the side wall of the through hole and contacting with the source electrode; The semiconductor device comprises a through hole, a groove, a metal layer, a semiconductor layer and a semiconductor layer, wherein the groove is positioned in the through hole, the groove is formed between the metal layer covering the side wall of the through hole and the metal layer in the through hole, which is in contact with the source electrode, the thickness of the metal layer covering the side wall of the through hole is reduced from the second surface to the direction of the semiconductor layer stack, and the thickness d3 of the metal layer in the through hole, which is in contact with the source electrode, is larger than the thickness d2 of the semiconductor layer stack.
  2. 2. The semiconductor device of claim 1, wherein the via includes a first via segment within the substrate and connecting the second surface, and a second via segment disposed across the substrate and the semiconductor stack, an end of the second via Duan Zidi segment distal from the second surface extending toward the semiconductor stack and through the semiconductor stack.
  3. 3. A semiconductor device, comprising: A substrate having a first surface and a second surface opposite to each other; A semiconductor stack on the first surface, the semiconductor stack having one side and another side opposite to each other, the one side of the semiconductor stack being in contact with the first surface; a source electrode located on the other surface of the semiconductor stack; The through hole extends from the second surface to the substrate and the semiconductor lamination along the thickness direction of the substrate in sequence to penetrate through the semiconductor lamination and expose the source electrode; A metal layer covering the second surface and extending to the side wall of the through hole and contacting with the source electrode; the thickness of the metal layer covered on the side wall of the through hole is reduced from the second surface to the direction of the semiconductor lamination; the semiconductor device comprises a through hole, a groove, a metal layer and a minimum horizontal dimension L1, wherein the groove is positioned in the through hole, the groove is formed between the metal layer covering the side wall of the through hole and the metal layer in the through hole, which is contacted with the source electrode, and the horizontal dimension of the bottom of the groove, which is close to one side of the semiconductor stack, is larger than the minimum horizontal dimension L1 of the groove when the cross section is parallel to the length direction of the grid and passes through the center of the through hole.
  4. 4. The semiconductor device of claim 3, wherein the bottom of the recess near one side of the semiconductor stack has a horizontal dimension that is the largest horizontal dimension of the recess, and wherein the via further comprises a second hole segment disposed across the substrate and the semiconductor stack, wherein an end of the second hole Duan Zidi that is distal from the second surface extends toward the semiconductor stack and through the entire semiconductor stack.
  5. 5. A semiconductor device, comprising: A substrate having a first surface and a second surface opposite to each other; A semiconductor stack on the first surface, the semiconductor stack having one side and another side opposite to each other, the one side of the semiconductor stack being in contact with the first surface; a source electrode located on the other surface of the semiconductor stack; The through hole comprises a first hole section and a second hole section, wherein the first hole section is positioned in the substrate and connected with the second surface, the second hole section is spanned in the substrate and the semiconductor laminated layer, and one end of the second hole Duan Zidi, which is far away from the second surface, extends to the semiconductor laminated layer and penetrates through the whole semiconductor laminated layer; A metal layer covering the second surface and extending to the side wall of the through hole and contacting with the source electrode; the thickness of the metal layer covered on the side wall of the through hole is reduced from the second surface to the direction of the semiconductor lamination; the ratio range of the depth h1 of the first hole section to the depth h3 of the second hole section on the substrate part is 1/5-3/h 1-3/4.
  6. 6. A semiconductor device, comprising: A substrate having a first surface and a second surface opposite to each other; A semiconductor stack on the first surface, the semiconductor stack having one side and another side opposite to each other, the one side of the semiconductor stack being in contact with the first surface; a source electrode located on the other surface of the semiconductor stack; The through hole comprises a first hole section and a second hole section, wherein the first hole section is positioned in the substrate and connected with the second surface, the second hole section is spanned in the substrate and the semiconductor laminated layer, and one end of the second hole Duan Zidi, which is far away from the second surface, extends to the semiconductor laminated layer and penetrates through the whole semiconductor laminated layer; A metal layer covering the second surface and extending to the side wall of the through hole and contacting with the source electrode; the thickness of the metal layer covered on the side wall of the through hole is reduced from the second surface to the direction of the semiconductor lamination; the relation between the thickness d2 of the semiconductor lamination and the depth h3 of the second hole section on the substrate part satisfies the condition that 5 d2≤h3≤235 d2。
  7. 7. A semiconductor device, comprising: A substrate having a first surface and a second surface opposite to each other; A semiconductor stack on the first surface, the semiconductor stack having one side and another side opposite to each other, the one side of the semiconductor stack being in contact with the first surface; a source electrode located on the other surface of the semiconductor stack; The through hole comprises a first hole section and a second hole section, wherein the first hole section is positioned in the substrate and connected with the second surface, the second hole section is spanned in the substrate and the semiconductor laminated layer, and one end of the second hole Duan Zidi, which is far away from the second surface, extends to the semiconductor laminated layer and penetrates through the whole semiconductor laminated layer; A metal layer covering the second surface and extending to the side wall of the through hole and contacting with the source electrode; the thickness of the metal layer covered on the side wall of the through hole is reduced from the second surface to the direction of the semiconductor lamination; the relation between the thickness d3 of the metal layer in the through hole, which is in contact with the source electrode, and the thickness d4 of the metal layer covering the second hole Duan Cebi is satisfied that d3 is equal to or greater than d4.
  8. 8. The semiconductor device according to any one of claims 1 to 7, wherein a difference between a maximum dimension W1 of the via and a minimum dimension W2 of the via is greater than 3 μm in a cross-sectional view parallel to a gate length direction and passing through a center of the via.
  9. 9. The semiconductor device according to any one of claims 1 to 7, wherein the minimum dimension W2 of the via hole has a value in a range of 10 μm≤W2≤45 μm in a cross section parallel to the gate length direction and passing through the center of the via hole.
  10. 10. The semiconductor device according to any one of claims 1 to 7, wherein the thickness d1 of the substrate is in a range of 40 μm or less and d1 or less and 120 μm or less, the substrate is a SiC substrate, the semiconductor device is a HEMT device, and the HEMT device comprises a heterojunction.
  11. 11. The semiconductor device according to any one of claims 1 to 7, wherein the thickness d2 of the semiconductor stack is in a range of 100 nm≤d2≤2500 nm.
  12. 12. The semiconductor device according to any one of claims 1 to 7, wherein at least one source electrode is provided with the via hole, a top view projected area defining a single source electrode on the other surface of the semiconductor stack is denoted as S, and a sum of end surface areas of all via holes located under the single source electrode formed at the other surface of the semiconductor stack is denoted as STV, 1.3< S/STV <20.
  13. 13. The semiconductor device according to any one of claims 1 to 7, wherein the number of the through holes provided under the single source electrode is plural, and a minimum distance W4 between adjacent through holes satisfies that W4 is not less than 6 μm.
  14. 14. The semiconductor device according to any one of claims 1 to 7, wherein the profile lines of both sides of the via hole in the cross section are formed by combining at least one of an inclined straight line, an inclined arc line, and a horizontal straight line, as viewed in a cross section parallel to the gate length direction and passing through the center of the via hole.
  15. 15. The semiconductor device of any one of claims 2, 4-7, wherein the depth h1 of the first hole segment is greater than the depth h2 of the second hole segment.
  16. 16. The semiconductor device according to any one of claims 2,4 to 7, wherein a first angle α formed between an extension line of the sidewall of the first hole section and the other surface of the semiconductor stack is larger than a second angle β formed between the second hole Duan Cebi and the other surface of the semiconductor stack.
  17. 17. The semiconductor device according to any one of claims 2 and 4 to 7, wherein the minimum horizontal aperture of the first hole section is equal to or larger than the maximum horizontal aperture of the second hole section.
  18. 18. A semiconductor device according to any one of claims 2, 4 to 7, wherein the relationship between the thickness d5 of the metal layer covering the sidewall of the first hole section and the thickness d6 of the metal layer covering the second surface satisfies that d5≤d6 <1.5 d5。
  19. 19. The semiconductor device according to any one of claims 2 and 4 to 7, wherein a thickness d3 of the metal layer in the via hole contacting the source electrode is 2 μm or more, a thickness d4 of the metal layer covering the second hole Duan Cebi is 2 μm or more, and a thickness d5 of the metal layer covering the sidewall of the first hole section is less than 8 μm.
  20. 20. A radio frequency module comprising the semiconductor device according to any one of claims 1 to 19.

Description

Semiconductor device and radio frequency module The application relates to a split application of an application patent application with the application date of 2025, 11, 19, the application number of 202511695092.4 and the application name of a semiconductor device and a radio frequency module. Technical Field The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a radio frequency module. Background Gallium nitride (GaN) high electron mobility transistor (HEMT, high Electron Mobility Transistor) has the advantages of high frequency, high voltage, high temperature and the like, is the future development direction of solid-state microwave power devices and power electronic devices, and is widely applied to the fields of 5G communication, radar, power electronics and the like. In a conventional silicon carbide (SiC) -based GaN HEMT rf device, in order to achieve a source electrode with a shortest path to ground to reduce parasitic inductance and provide a vertical low thermal resistance heat dissipation path, a design of connecting a source electrode active region with a backside ground metal layer via a backside hole is generally adopted to achieve electrical connection and thermal conduction. However, in the conventional design of providing the backside ground metal layer in the backside hole, the difference in thermal expansion coefficient between different materials is large, which easily causes a problem of significant thermal stress between the backside ground metal layer and the substrate/semiconductor stack. Disclosure of Invention The invention provides a semiconductor device, which can solve at least one problem in the background art by design so as to improve the comprehensive performance and reliability of HEMTs. The invention provides a semiconductor device which comprises a substrate, a semiconductor lamination layer, a source electrode, a through hole, a metal layer, a groove and a groove, wherein the substrate is provided with a first surface and a second surface which are opposite to each other, the semiconductor lamination layer is arranged on the first surface and provided with one surface and the other surface which are opposite to each other, one surface of the semiconductor lamination layer is contacted with the first surface, the source electrode is arranged on the other surface of the semiconductor lamination layer, the through hole extends from the second surface to penetrate through the semiconductor lamination layer to expose the source electrode along the thickness direction of the substrate, the metal layer covers the second surface and extends to the side wall of the through hole and is contacted with the source electrode, the groove is arranged in the through hole, the groove is formed between the metal layer covering the side wall of the through hole and the metal layer contacting with the source electrode in the through hole, the thickness of the metal layer covering the side wall of the through hole is reduced from the second surface to the direction of the semiconductor lamination layer, and the thickness d3 of the metal layer contacting with the source electrode in the through hole is larger than the thickness d2 of the semiconductor lamination layer. Through the arrangement, the problem of thermal stress between the metal layer and the substrate/semiconductor lamination can be relieved, CTE mismatch is improved, enough transverse conduction cross-section area of back electrode metal can be guaranteed, the semiconductor lamination to the back electrode can form a transverse shortest current conduction path, the carrier conduction path is shortened, the conduction area is increased, on-resistance and current loss are effectively reduced, the transverse conduction area between the bottom of the source electrode and the metal layer is guaranteed, carriers are enabled to be in high-efficiency contact with the metal layer at the bottom of the source electrode, and the current flowing capacity of the device is improved. Further, the via includes a first via segment located in the substrate and connected to the second surface, and a second via segment straddling the substrate and the semiconductor stack, wherein an end of the second via Duan Zidi, remote from the second surface, extends toward the semiconductor stack and extends through the entire semiconductor stack. The invention provides a semiconductor device which comprises a substrate, a semiconductor lamination layer, a source electrode, a through hole, a metal layer, a groove and a groove, wherein the substrate is provided with a first hole section which is positioned in the substrate and is connected with a second surface, the metal layer covers the second surface and extends to the side wall of the through hole and is contacted with the source electrode, the thickness of the metal layer which covers the side wall of the through hole is reduc