CN-122028464-A - Semiconductor structure, manufacturing method thereof, memory and electronic equipment

Abstract

The embodiment of the disclosure discloses a semiconductor structure, a manufacturing method thereof, a memory and electronic equipment. The semiconductor structure comprises a channel structure, a grid structure, a doping structure and a conductive structure, wherein the channel structure extends along a first direction, the grid structure surrounds the channel structure, the doping structure is located at two ends of the channel structure in the first direction, the doping structure comprises a first hole extending along a second direction, the second direction is perpendicular to the first direction, and the conductive structure is located in the first hole at least partially and covers the first inner wall of the first hole.

Inventors

• LI YUKE
• DENG XUEJIAN
• WANG GUILEI

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241112

Claims (20)

1. 1. A semiconductor structure, comprising: A channel structure extending in a first direction; A gate structure surrounding the channel structure; The doped structure is positioned at two ends of the channel structure in the first direction and comprises a first hole extending along a second direction, wherein the second direction is perpendicular to the first direction; and the conductive structure is at least partially positioned in the first hole and covers the first inner wall of the first hole.
2. 2. The semiconductor structure of claim 1, wherein the conductive structure further covers at least a first outer wall of the doped structure, wherein the first outer wall comprises a surface of the doped structure other than the first inner wall.
3. 3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: the barrier structure comprises a second hole extending along the second direction, and the second hole is communicated with the first hole; The conductive structure is also located in the second hole and covers a second inner wall of the second hole.
4. 4. The semiconductor structure of claim 3, wherein said conductive structure further covers at least a second outer wall of said barrier structure, wherein said second outer wall comprises a surface of said barrier structure other than said second inner wall.
5. 5. The semiconductor structure of claim 3, wherein the conductive structure comprises: an adhesive layer covering at least the first inner wall and the second inner wall; And a conductive layer covering the adhesive layer.
6. 6. The semiconductor structure of claim 1, wherein the channel structure comprises: a plurality of sub-channel structures stacked along the second direction; the gate structure surrounds each of the sub-channel structures.
7. 7. The semiconductor structure of claim 6, wherein the semiconductor structure further comprises: and a first isolation structure positioned between the gate structure and the doped structure and positioned between the sub-channel structures adjacent in the second direction.
8. 8. The semiconductor structure of claim 6, wherein the gate structure comprises: a gate dielectric layer surrounding each of the sub-channel structures; And the gate electrode layer surrounds the gate dielectric layer.
9. 9. The semiconductor structure of claim 1, wherein the semiconductor structure comprises: a plurality of the channel structures arranged at intervals along the first direction; Wherein two channel structures adjacent along the first direction are connected with the same doping structure.
10. 10. A method of fabricating a semiconductor structure, the method comprising: Forming a channel structure extending along a first direction; forming a gate structure surrounding the channel structure; Forming a doped structure at two ends of the channel structure in the first direction, wherein the doped structure comprises a first hole extending along a second direction, and the second direction is perpendicular to the first direction; a conductive structure is formed at least partially within the first aperture and covering a first inner wall of the first aperture.
11. 11. The method of manufacturing of claim 10, wherein forming a doped structure at both ends of the channel structure in the first direction comprises: forming an initial doping structure at two ends of the channel structure in the first direction; forming the first hole in the initial doping structure to form the doping structure; the forming a conductive structure at least partially within and covering a first inner wall of the first hole, comprising: forming the conductive structure at least partially in the first hole and covering the first inner wall and at least one first outer wall of the doped structure, wherein the first outer wall comprises a surface of the doped structure other than the first inner wall.
12. 12. The method of manufacturing according to claim 11, wherein the method further comprises: Forming an initial blocking structure on the top surface of the initial doping structure in the second direction; Forming a second hole penetrating through the initial blocking structure, and forming blocking structures by the rest of the initial blocking structures; the forming the first hole in the initial doping structure to form the doping structure includes: The first hole and the doping structure are formed by removing part of the initial doping structure through the second hole, and the blocking structure is connected with the doping structure along the second direction, and the first hole is communicated with the second hole; the forming a conductive structure at least partially within and covering a first inner wall of the first hole, comprising: The conductive structure is formed at least partially in the first and second holes and covers the first and second inner walls of the second hole.
13. 13. The method of manufacturing of claim 12, wherein the forming the conductive structure at least partially in the first and second holes and covering the first and second inner walls of the second hole comprises: Forming the conductive structure at least partially in the first and second holes and covering at least one second outer wall of the first inner wall, the second inner wall, and the barrier structure, wherein the second outer wall includes a surface of the barrier structure other than the second inner wall.
14. 14. The method of manufacturing of claim 12, wherein the forming the conductive structure at least partially in the first and second holes and covering the first and second inner walls of the second hole comprises: forming an adhesive layer covering at least the first inner wall and the second inner wall; A conductive layer is formed overlying the adhesion layer.
15. 15. The method of manufacturing of claim 10, wherein forming the channel structure extending in the first direction comprises: forming a stacked structure, wherein the stacked structure comprises a plurality of sub-channel layers and a plurality of first sacrificial layers which are alternately stacked along the second direction; Forming a plurality of first trenches extending in the first direction and a plurality of second trenches extending in a third direction in the stacked structure; the first groove and the second groove divide the sub-channel layer into a plurality of sub-channel structures, and the plurality of sub-channel structures stacked along the second direction form the channel structure; The forming a doped structure at two ends of the channel structure in the first direction includes: The doping structure is formed in the second trenches at both ends of the channel structure in the first direction.
16. 16. The method of manufacturing according to claim 15, wherein the method further comprises: Removing a part of the first sacrificial layer along the first direction through the second groove to form a first sacrificial structure and a groove between the first sacrificial structure and the second groove; a first isolation structure is formed in the recess.
17. 17. The method of manufacturing of claim 16, wherein forming the gate structure surrounding the channel structure comprises: removing the first sacrificial structures to form gaps exposing the sub-channel structures, wherein the gaps are at least partially positioned between two adjacent first isolation structures; forming a gate dielectric layer surrounding each sub-channel structure in the gap; and forming a gate electrode layer surrounding the gate dielectric layer.
18. 18. The method of manufacturing according to claim 15, wherein the method further comprises: forming a second isolation structure in the first groove, wherein the second isolation structure and the doping structure are alternately arranged along the third direction; the forming a conductive structure at least partially within and covering a first inner wall of the first hole, comprising: forming a second sacrificial structure in the first hole; Removing the second sacrificial structure and a part of the second isolation structure adjacent to the doped structure to form a third hole, wherein the third hole exposes the first inner wall and the first outer wall of the doped structure; The conductive structure is formed in the third hole to cover the first inner wall and the first outer wall.
19. 19. A memory comprising an array of memory cells and peripheral circuitry, wherein the array of memory cells and/or the peripheral circuitry comprises the semiconductor structure of any one of claims 1 to 9 or the semiconductor structure formed by the method of any one of claims 10 to 18.
20. 20. An electronic device comprising a memory and/or control circuit comprising the semiconductor structure of any one of claims 1 to 9 or formed by the method of any one of claims 10 to 18.

Description

Semiconductor structure, manufacturing method thereof, memory and electronic equipment Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, and relates to a semiconductor structure, a manufacturing method thereof, a memory and electronic equipment. Background In recent years, the semiconductor integrated circuit industry has experienced rapid growth. With the continuous progress of semiconductor manufacturing process, the feature size of semiconductor devices is continuously reduced, and the miniaturization of the device size causes various problems such as parasitic capacitance increase and contact resistance increase. Disclosure of Invention The present disclosure provides a semiconductor structure, a method of manufacturing the same, a memory, and an electronic device. In a first aspect, the disclosure provides a semiconductor structure comprising a channel structure extending along a first direction, a gate structure surrounding the channel structure, a doped structure located at two ends of the channel structure in the first direction, the doped structure comprising a first hole extending along a second direction, wherein the second direction is perpendicular to the first direction, and a conductive structure located at least partially in the first hole and covering a first inner wall of the first hole. In some embodiments, the conductive structure further covers at least one first outer wall of the doped structure, wherein the first outer wall includes a surface of the doped structure other than the first inner wall. In some embodiments, the semiconductor structure further includes a blocking structure connected to the doped structure along the second direction, the blocking structure including a second hole extending along the second direction, the second hole in communication with the first hole, the conductive structure further located in the second hole and covering a second inner wall of the second hole. In some embodiments, the conductive structure further covers at least one second outer wall of the barrier structure, wherein the second outer wall includes a surface of the barrier structure other than the second inner wall. In some embodiments, the conductive structure includes an adhesion layer covering at least the first inner wall and the second inner wall, and a conductive layer covering the adhesion layer. In some embodiments, the channel structure includes a plurality of sub-channel structures stacked along the second direction, the gate structure surrounding each of the sub-channel structures. In some embodiments, the semiconductor structure further includes a first isolation structure between the gate structure and the doped structure and between the sub-channel structures adjacent in the second direction. In some embodiments, the gate structure comprises a gate dielectric layer surrounding each sub-channel structure, and a gate electrode layer surrounding the gate dielectric layer. In some embodiments, the semiconductor structure comprises a plurality of channel structures arranged at intervals along the first direction, wherein two adjacent channel structures along the first direction are connected with the same doped structure. In a second aspect, the present disclosure provides a method of manufacturing a semiconductor structure, the method comprising forming a channel structure extending along a first direction, forming a gate structure surrounding the channel structure, forming a doped structure at both ends of the channel structure in the first direction, the doped structure comprising a first hole extending along a second direction, wherein the second direction is perpendicular to the first direction, and forming a conductive structure at least partially located in the first hole and covering a first inner wall of the first hole. In some embodiments, the forming of the doped structure at both ends of the channel structure in the first direction includes forming an initial doped structure at both ends of the channel structure in the first direction, forming the first hole in the initial doped structure to form the doped structure, forming a conductive structure at least partially in the first hole and covering a first inner wall of the first hole includes forming the conductive structure at least partially in the first hole and covering the first inner wall and at least one first outer wall of the doped structure, wherein the first outer wall includes a surface of the doped structure other than the first inner wall. In some embodiments, the method further includes forming an initial blocking structure on a top surface of the initial doping structure in the second direction, forming a second hole through the initial blocking structure, the remaining initial blocking structure constituting a blocking structure, the forming the first hole in the initial doping structure to form the doping structure including removing a portion of the ini