CN-122028465-A - Semiconductor structure, manufacturing method thereof, semiconductor device and electronic equipment

Abstract

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof, a semiconductor device and electronic equipment. The semiconductor structure comprises a first channel structure and a second channel structure which are stacked in a first direction, a grid structure comprising a first part and a second part which are arranged along the first direction, wherein the first channel structure surrounds the first part, the second channel structure surrounds the second part, first doping structures are arranged at two ends of the first channel structure in the second direction, the first channel structure, the first part and the first doping structures form a first transistor, the second direction is perpendicular to the first direction, second doping structures are arranged at two ends of the second channel structure in the second direction, and the second channel structure, the second part and the second doping structures form a second transistor.

Inventors

• LI YUKE
• MAO SHUJUAN

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241112

Claims (20)

1. 1. A semiconductor structure, comprising: A first channel structure and a second channel structure stacked in a first direction; A gate structure including a first portion and a second portion arranged along the first direction; the first channel structure surrounds the first portion, and the second channel structure surrounds the second portion; the first doping structures are positioned at two ends of the first channel structure in the second direction; the first channel structure, the first part and the first doping structure form a first transistor, and the second direction is perpendicular to the first direction; The second doping structures are positioned at two ends of the second channel structure in the second direction; the second channel structure, the second portion, and the second doped structure constitute a second transistor.
2. 2. The semiconductor structure of claim 1, wherein the first channel structure comprises at least one first sub-channel structure disposed stacked in the first direction; And/or the number of the groups of groups, The second channel structure includes at least one second sub-channel structure disposed in a stack in the first direction.
3. 3. The semiconductor structure of claim 1, wherein the gate structure comprises: the conductive structure comprises a first side wall and a second side wall which are arranged along the first direction; The first functional layer and the part of the conductive structure surrounded by the first functional layer form the first part; and the second functional layer and the part of the conductive structure surrounded by the second functional layer form the second part.
4. 4. The semiconductor structure of claim 3, wherein the first sidewall and the second sidewall are spaced apart along the first direction, the conductive structure further comprising a third sidewall between the first sidewall and the second sidewall; the semiconductor structure further includes: and the first isolation structure is positioned between the first functional layer and the second functional layer and surrounds the third side wall.
5. 5. The semiconductor structure of claim 3, wherein the first functional layer comprises: a first conductive layer covering the first sidewall; A first dielectric layer covering the first conductive layer; The second functional layer includes: a second conductive layer covering the second sidewall; and the second dielectric layer covers the second conductive layer.
6. 6. The semiconductor structure of claim 3, wherein the first channel structure further covers an end face of the gate structure that is remote from the second channel structure in the first direction; the first functional layer also covers an end face of the conductive structure away from the second channel structure in the first direction.
7. 7. The semiconductor structure of claim 1, wherein a dimension of the first channel structure in the second direction is greater than a dimension of the second channel structure in the second direction.
8. 8. The semiconductor structure of claim 7, wherein the first doped structure comprises a first source structure and a first drain structure, the first source structure and the first drain structure being located at opposite ends of the first channel structure in the second direction, respectively; The second doping structure comprises a second source electrode structure and a second drain electrode structure, wherein the second source electrode structure and the second drain electrode structure are respectively positioned at two ends of the second channel structure in the second direction; Wherein the first drain structure is aligned and connected with the second drain structure in the first direction.
9. 9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises: a first contact structure located at one side of the first source structure near the second channel structure in the first direction; And the second isolation structure at least covers the side wall of one side of the first contact structure, which is close to the second channel structure.
10. 10. A method of fabricating a semiconductor structure, the method comprising: forming a first channel structure and a second channel structure stacked in a first direction; forming a gate structure comprising a first portion and a second portion arranged along the first direction, the first channel structure surrounding the first portion, the second channel structure surrounding the second portion; Forming a first doping structure at two ends of the first channel structure in a second direction, wherein the first channel structure, the first part and the first doping structure form a first transistor; and forming second doping structures at two ends of the second channel structure in the second direction, wherein the second channel structure, the second part and the second doping structures form a second transistor.
11. 11. The method of manufacturing of claim 10, wherein forming the first channel structure comprises: Forming at least one first sub-channel structure stacked in the first direction; And/or the number of the groups of groups, Forming the second channel structure includes: at least one second sub-channel structure is formed stacked in the first direction.
12. 12. The method of manufacturing of claim 10, wherein forming the gate structure comprises: Forming a first channel layer and a second channel layer stacked in the first direction; forming a hole penetrating the second channel layer along the first direction and extending into the first channel layer, wherein the hole comprises a first inner wall and a second inner wall which are arranged along the first direction; Forming a first functional layer covering the first inner wall; forming a second functional layer covering the second inner wall; forming a conductive structure in the hole in which the first functional layer and the second functional layer are formed; the first functional layer and the part of the conductive structure surrounded by the first functional layer form the first part, and the second functional layer and the part of the conductive structure surrounded by the second functional layer form the second part.
13. 13. The method of manufacturing according to claim 12, wherein the first inner wall and the second inner wall are spaced apart along the first direction, the hole further comprising a third inner wall between the first inner wall and the second inner wall; the method further comprises the steps of: A first isolation structure is formed to cover the third inner wall and between the first functional layer and the second functional layer.
14. 14. The method of manufacturing according to claim 12, wherein the forming a first functional layer covering the first inner wall includes: forming a first dielectric layer covering the first inner wall; forming a first conductive layer covering the first dielectric layer; The forming a second functional layer covering the second inner wall includes: forming a second dielectric layer covering the second inner wall; And forming a second conductive layer covering the second dielectric layer.
15. 15. The method of manufacturing of claim 12, wherein the first inner wall includes sidewalls and a bottom surface of the hole exposing a portion of the first channel layer; The forming a first functional layer covering the first inner wall includes: Forming the first functional layer covering a sidewall and a bottom surface of the hole exposing a portion of the first channel layer.
16. 16. The method of manufacturing according to claim 12, wherein the forming of the first channel structure and the second channel structure disposed in a stack in the first direction includes: Forming a first contact hole penetrating the second channel layer and extending into the first channel layer; Forming a second contact hole penetrating through the second channel layer and extending into the first channel layer, wherein the first contact hole and the second contact hole are respectively positioned at two sides of the gate structure in the second direction; Forming a third contact hole penetrating through the second channel layer, wherein the third contact hole is positioned between the first contact hole and the gate structure in the second direction; the second channel layer is positioned between the third contact hole and the second contact hole to form the second channel structure, and the first channel layer is positioned between the first contact hole and the second contact hole to form the first channel structure.
17. 17. The method of manufacturing of claim 16, wherein forming a first doped structure at both ends of the first channel structure in the second direction comprises: Forming a first source electrode structure and a first drain electrode structure in the first contact hole and the second contact hole respectively, wherein the top surface of the first source electrode structure and the top surface of the first drain electrode structure are lower than the bottom surface of the second channel structure; Forming a second doping structure at two ends of the second channel structure in the second direction, including: Forming a second drain structure in the second contact hole in which the first drain structure is formed; and forming a second source electrode structure in the third contact hole.
18. 18. The method of manufacturing according to claim 16, wherein the method further comprises: forming a second isolation structure in the first contact hole, wherein the second isolation structure at least covers the side wall of the first contact hole, which is close to one side of the second channel structure; A first contact structure is formed in the first contact hole in which the second isolation structure is formed.
19. 19. A semiconductor device comprising the semiconductor structure of any one of claims 1 to 9 or comprising the semiconductor structure formed by the method of any one of claims 10 to 18.
20. 20. An electronic device comprising the semiconductor device according to claim 19.

Description

Semiconductor structure, manufacturing method thereof, semiconductor device and electronic equipment Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, and relates to, but is not limited to, a semiconductor structure, a manufacturing method thereof, a semiconductor device and electronic equipment. Background In recent years, the semiconductor integrated circuit industry has experienced rapid growth. With the continuous progress of semiconductor manufacturing processes, the feature size of semiconductor devices is continuously reduced, and the miniaturization of device size causes performance degradation, and the increase of metal interconnection density causes signal delay. Currently, semiconductor structures are stacked in a vertical direction, which is an important development direction. However, the vertically stacked semiconductor structure still has the problems of high process difficulty, low yield, and the like. Disclosure of Invention The present disclosure provides a semiconductor structure, a method of manufacturing the same, a semiconductor device, and an electronic apparatus. In a first aspect, the disclosure provides a semiconductor structure comprising a first channel structure and a second channel structure stacked in a first direction, a gate structure comprising a first portion and a second portion arranged along the first direction, the first channel structure surrounding the first portion and the second channel structure surrounding the second portion, a first doping structure located at two ends of the first channel structure in a second direction, the first channel structure, the first portion and the first doping structure forming a first transistor, the second direction being perpendicular to the first direction, a second doping structure located at two ends of the second channel structure in the second direction, and the second channel structure, the second portion and the second doping structure forming a second transistor. In some embodiments, the first channel structure comprises at least one first sub-channel structure arranged in a stack in the first direction, and/or the second channel structure comprises at least one second sub-channel structure arranged in a stack in the first direction. In some embodiments, the gate structure comprises a conductive structure extending along the first direction, the conductive structure comprises a first side wall and a second side wall arranged along the first direction, a first functional layer surrounds the first side wall, the first functional layer and a part of the conductive structure surrounded by the first functional layer form the first part, a second functional layer surrounds the second side wall, and the second functional layer and a part of the conductive structure surrounded by the second functional layer form the second part. In some embodiments, the first and second sidewalls are spaced apart along the first direction, the conductive structure further includes a third sidewall between the first and second sidewalls, and the semiconductor structure further includes a first isolation structure between the first and second functional layers and surrounding the third sidewall. In some embodiments, the first functional layer comprises a first conductive layer covering the first side wall, a first dielectric layer covering the first conductive layer, and the second functional layer comprises a second conductive layer covering the second side wall, and a second dielectric layer covering the second conductive layer. In some embodiments, the first channel structure also covers an end face of the gate structure that is remote from the second channel structure in the first direction, and the first functional layer also covers an end face of the conductive structure that is remote from the second channel structure in the first direction. In some embodiments, a dimension of the first channel structure in the second direction is greater than a dimension of the second channel structure in the second direction. In some embodiments, the first doped structure includes a first source structure and a first drain structure, the first source structure and the first drain structure are located at two ends of the first channel structure in the second direction, respectively, the second doped structure includes a second source structure and a second drain structure, the second source structure and the second drain structure are located at two ends of the second channel structure in the second direction, respectively, wherein the first drain structure and the second drain structure are aligned and connected in the first direction. In some embodiments, the semiconductor structure further comprises a first contact structure located on one side of the first source structure, which is close to the second channel structure in the first direction, and a second isolation structure at least covering the side wal