CN-122028466-A - Semiconductor device and method for manufacturing the same

CN122028466ACN 122028466 ACN122028466 ACN 122028466ACN-122028466-A

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. A gate electrode is formed in the trench. An insulating film is formed on the gate electrode to protrude from an upper surface of the semiconductor substrate. Sidewall spacers are formed on side surfaces of the insulating film and on an upper surface of the semiconductor substrate. Holes are formed in portions of the semiconductor substrate exposed from the insulating film and the sidewall spacers. A barrier metal film is formed in the hole. The second opening width of the hole at a second location corresponding to a location of the junction surface between the body region and the source region is greater than the first opening width of the hole at a first location corresponding to a location of the upper surface of the semiconductor substrate. The barrier metal film includes a silicide film and a metal film.

Inventors

Mu Xingsheng

Assignees

瑞萨电子株式会社

Dates

Publication Date: 20260512
Application Date: 20251014
Priority Date: 20241112

Claims (16)

1. A semiconductor device, comprising: A semiconductor substrate of a first conductivity type having an upper surface; A trench formed in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate; a gate electrode formed in the trench; An insulating film formed on the gate electrode to protrude from the upper surface of the semiconductor substrate; A body region of a second conductivity type opposite to the first conductivity type, the body region being formed in a portion of the semiconductor substrate exposed from the insulating film; a source region of the first conductivity type formed in the body region; A sidewall spacer formed on a side surface of the insulating film and the upper surface of the semiconductor substrate; A hole formed in a portion of the semiconductor substrate exposed from the insulating film and the sidewall spacer to penetrate the source region and reach the body region, and A barrier metal film formed in the hole, Wherein an opening width of the hole at a second position of a junction surface between the body region and the source region is larger than an opening width of the hole at a first position of the upper surface of the semiconductor substrate, and Wherein the barrier metal film comprises: A silicide film formed in the hole, and And a second metal film formed on the silicide film.
2. The semiconductor device according to claim 1, Wherein an opening width of the hole at a fourth position of an upper surface of the barrier metal film formed over a deepest portion of the hole is smaller than an opening width of the hole at the second position and larger than an opening width of the hole at the first position.
3. The semiconductor device according to claim 2, Wherein a thickness of the barrier metal film formed in the hole extending from the first location to the fourth location is less than a thickness of the barrier metal film formed in the hole extending from the fourth location to the deepest portion of the hole.
4. The semiconductor device according to claim 1, Wherein the barrier metal film includes a third metal film formed in the hole to cover the second metal film and the silicide film, and Wherein the thickness of the third metal film is smaller than the thickness of the silicide film and the thickness of the second metal film.
5. The semiconductor device of claim 4, comprising: A tungsten film formed in the hole via the barrier metal film, Wherein the silicide film is a titanium silicide film, Wherein the second metal film is a titanium nitride film, and Wherein the third metal film is a titanium nitride film.
6. A method of manufacturing a semiconductor device, the method comprising the steps of: (a) Preparing a semiconductor substrate of a first conductivity type, the semiconductor substrate having an upper surface; (b) Forming a trench in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate after (a); (c) After (b), forming a gate electrode in the trench; (d) After (c), forming an insulating film in the trench and on the gate electrode; (e) After (d), performing an etching process on the semiconductor substrate using the insulating film as a mask to lower a position of the upper surface of the semiconductor substrate to a position lower than the upper surface of the insulating film; (f) After (e), forming a body region of a second conductivity type in a portion of the semiconductor substrate exposed from the insulating film, the second conductivity type being opposite to the first conductivity type; (g) After (f), forming a source region of the first conductivity type in the body region; (h) After (g), forming sidewall spacers on side surfaces of the insulating film and on the upper surface of the semiconductor substrate; (i) After (h), performing an etching process on the semiconductor substrate using the insulating film and the sidewall spacers as a mask to form holes penetrating the source region and reaching the body region, and (J) After (i), forming a barrier metal film in the hole, Wherein prior to (j), an opening width of the hole at a second location of a junction surface between the body region and the source region is greater than an opening width of the hole at a first location of the upper surface of the semiconductor substrate, and Wherein, (j) comprises: (j1) Forming a first metal film in the hole using a sputtering method; (j2) After (j 1), forming a second metal film on the first metal film using a sputtering method, and (J3) After (j 2), performing a heat treatment to react the first metal film with silicon contained in the semiconductor substrate, thereby forming a silicide film.
7. The method according to claim 6, wherein the method comprises, Wherein after (j), the opening width of the hole at the second location is greater than the opening width of the hole at the first location.
8. The method according to claim 6, wherein the method comprises, Wherein prior to (j), the aperture has an opening width at a third location of 30 nm above the deepest portion of the aperture that is less than the opening width of the aperture at the second location and greater than the opening width of the aperture at the first location.
9. The method according to claim 8, wherein the method comprises, Wherein after (j 2) and before (j 3), a thickness of the barrier metal film formed in the hole extending from the first location to a fourth location is less than a thickness of the barrier metal film formed in the hole extending from the fourth location to the deepest portion of the hole.
10. The method according to claim 6, wherein the method comprises, Wherein after (j), an opening width of the hole at a fourth position of an upper surface of the barrier metal film formed over a deepest portion of the hole is smaller than an opening width of the hole at the second position and larger than an opening width of the hole at the first position.
11. The method according to claim 10, Wherein after (j), a thickness of the barrier metal film formed in the hole extending from the first location to the fourth location is less than a thickness of the barrier metal film formed in the hole extending from the fourth location to the deepest portion of the hole.
12. The method according to claim 6, wherein the method comprises, Wherein (j) comprises: (j4) After (j 3), forming a third metal film in the hole using a CVD method to cover the second metal film and the silicide film, Wherein the thickness of the third metal film is smaller than the thickness of the silicide film and the thickness of the second metal film.
13. The method of claim 12, comprising: (k) After (j), forming a tungsten film in the hole via the barrier metal film using a CVD method, Wherein the first metal film is a titanium film, Wherein the silicide film is a titanium silicide film, Wherein the second metal film is a titanium nitride film, and Wherein the third metal film is a titanium nitride film.
14. The method according to claim 6, wherein the method comprises, Wherein the etching treatment in (i) comprises an anisotropic etching treatment using Cl 2 gas and O 2 gas, and Wherein the value of "the flow rate of Cl 2 gas/the flow rate of O 2 gas" is 6 or more and 13 or less.
15. The method according to claim 14, Wherein the Cl 2 gas flow rate is 60 sccm or more and 80 sccm or less, and Wherein the flow rate of the O 2 gas is 6 to sccm inclusive and 10 to sccm inclusive.
16. The method according to claim 14, Wherein the etching treatment in (i) comprises an isotropic etching treatment using buffered hydrofluoric acid.

Description

Semiconductor device and method for manufacturing the same Cross Reference to Related Applications The disclosure of japanese patent application No. 2024-197308, filed on 11/12 of 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a method of manufacturing a semiconductor device in which a gate electrode is mounted in a trench. Background In a semiconductor device equipped with a semiconductor element such as a power MOSFET (metal oxide semiconductor field effect transistor), a trench gate structure is applied at a position where a gate electrode is formed in a trench. In the semiconductor substrate at the trench side surface, a body region is formed, and in the body region, a source region is formed. A portion of the body region adjacent to the gate electrode via the gate insulating film serves as a channel region. Typically, to electrically connect the body region and the source region to the source electrode, a hole is formed through the source region and to the body region. The disclosed techniques are listed below. [ Patent document 1] Japanese patent laid-open No. 2002-246596 [ Patent document 2] Japanese patent application laid-open No. 2024-128687 For example, patent document 1 discloses a technique of forming holes in a self-aligned manner. First, a cap film made of an insulating film is formed in the trench and on the gate electrode. Next, an etching process is performed by using the cap film as a mask, so that the upper surface of the semiconductor substrate is recessed. As a result, the cap film protrudes from the upper surface of the semiconductor substrate. Then, a body region is formed in the semiconductor substrate exposed from the cap film, and a source region is formed in the body region. Next, sidewall spacers are formed on the side surfaces of the cover film. Subsequently, a hole is formed in the semiconductor substrate by performing an etching process using the cap film and the sidewall spacer as masks. Then, a high-concentration contact region is formed in the semiconductor substrate near the bottom portion of the hole. Finally, a source electrode is formed on the cap film and the sidewall spacer to fill the hole. As shown in patent document 2, there is also known a technique of forming a plug in a hole and then forming a source electrode to be electrically connected with the plug. The plug is formed of a laminated film including a barrier metal film and a main conductive film. In patent document 2, a laminated film including a metal film and a metal nitride film is used as a barrier metal film. The metal film is a titanium film, and the metal nitride film is a titanium nitride film. First, a metal film is formed in a hole. Next, a metal nitride film is formed on the metal film. Then, a silicide film is formed by reacting the metal film with silicon contained in the semiconductor substrate by heat treatment. Subsequently, a tungsten film is formed to fill the hole via such a barrier metal film. Disclosure of Invention In recent years, with miniaturization of semiconductor devices, it has been demanded to reduce the opening width of holes. Therefore, when the silicide film is formed at the side portion of the hole, it tends to be formed in the vicinity of the channel region. In addition, during the formation of the silicide film, there is a problem in that aggregation occurs in the silicide film, and stress from the silicide film may cause cracks in the metal nitride film. These problems can reduce the reliability of the semiconductor device. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. A brief summary of exemplary embodiments disclosed in the present application is as follows. In one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type having an upper surface, a trench formed in the semiconductor substrate, a gate electrode formed in the trench, an insulating film formed on the gate electrode to protrude from the upper surface of the semiconductor substrate, a body region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate, a source region of the first conductivity type formed in the body region, sidewall spacers formed on side surfaces of the insulating film and on the upper surface of the semiconductor substrate, a hole formed in a portion of the semiconductor substrate exposed from the insulating film and the sidewall spacers to penetrate the source region and reach the body region, and a barrier metal film formed in the hole. The opening width of the hole at a second position corresponding to the position of the junction surface between the body region and the source region is larger than the opening width of