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CN-122028467-A - Bulk potential optimization structure of thin silicon film SOI MOSFET and preparation method thereof

CN122028467ACN 122028467 ACN122028467 ACN 122028467ACN-122028467-A

Abstract

The invention discloses a bulk potential optimization structure of a thin-film SOI MOSFET and a preparation method thereof, belonging to the field of semiconductor device preparation. The SOI substrate comprises a top silicon layer, an oxygen burying layer, a supporting layer, a body potential modulation region, a channel region, an insulating medium layer, a grid electrode, a source drain region and a doped element type of the channel region, wherein the top silicon layer, the oxygen burying layer and the supporting layer form an SOI substrate material together, the body potential modulation region is located in the top silicon layer, the bottom of the body potential modulation region is connected with the oxygen burying layer, the channel region is located in the top silicon layer and above the body potential modulation region, the insulating medium layer is located above the outside of the top silicon layer, the grid electrode is located on the insulating medium layer, the source drain region is located in the top silicon layer and is located on two sides of the body potential modulation region and the channel region, and the doped element type of the channel region is identical to that of the body potential modulation region. The invention introduces the body potential modulation region, reduces the resistance of the body region of the device, is beneficial to fixing the body region potential, reduces the body effect of the device, simplifies the circuit design, introduces impurity ions at two sides of the interface between the top silicon and the buried oxide layer, improves the hole concentration near the interface, inhibits the influence of radiation induced holes to a certain extent, reduces the characteristic degradation degree such as the threshold drift of the device, and improves the total dose resistance of the device.

Inventors

  • ZHAO XIAOSONG
  • WANG XINGHONG
  • GU XIANG

Assignees

  • 中国电子科技集团公司第五十八研究所

Dates

Publication Date
20260512
Application Date
20251216

Claims (8)

  1. 1. The body potential optimizing structure of the thin silicon film SOIMOSFET is characterized by comprising top silicon (1), a buried oxide layer (2), a supporting layer (3), a body potential modulation region (4), a channel region (5), an insulating medium layer (6), a grid electrode (7) and a source-drain region (8), The top silicon (1), the buried oxide layer (2) and the support layer (3) together form an SOI substrate material; the body potential modulation region (4) is positioned in the top silicon (1) and is positioned at the bottom of the body potential modulation region and connected with the oxygen buried layer (2); The channel region (5) is positioned in the top layer silicon (1) and above the body potential modulation region (4); the insulating medium layer (6) is positioned above the outer part of the top silicon layer (1); the grid electrode (7) is positioned on the insulating medium layer (6); the source/drain region (8) is positioned in the top silicon (1) and is positioned at two sides of the body potential modulation region (4) and the channel region (5); the doping element type of the channel region (5) is the same as that of the bulk potential modulation region (5).
  2. 2. Bulk potential optimizing structure of a thin-film silicon soi fet according to claim 1, characterized in that the thickness of the top silicon (1) is 1 to 500 nm and the thickness of the buried oxide layer (2) is 5 to 10000 nm.
  3. 3. The bulk potential optimizing structure of the thin-film silicon-on-insulator soimofet according to claim 1, characterized in that the bulk potential modulating region (4) is formed by ion implantation of impurity ions, the doping type is P-type or N-type, the doping element is phosphorus, boron, indium or arsenic or other group iii-v elements, and the doping concentration is 0-1E20/cm -3 .
  4. 4. A bulk potential optimizing structure of a thin-film silicon soi fet according to claim 1, characterized in that the channel region (5) is formed by ion implantation or diffusion of impurity ions, the doping type is P-type or N-type, the doping element is phosphorus, boron, indium or arsenic or other group iii-v elements, and the doping concentration is 0-1E20/cm -3 .
  5. 5. The bulk potential optimization structure of the thin-film silicon SOIMOSFET according to claim 1, wherein the insulating dielectric layer (6) is SiO 2 , oxynitride, tiO 2 、HfO 2 、Si 3 N 4 、ZrO 2 、Ta 2 O 5 , barium strontium titanate BST, lead zirconate titanate piezoelectric ceramic PZT or Al 2 O 3 , and the thickness is 0.1-20 nanometers.
  6. 6. The bulk potential optimizing structure of a thin-film silicon soi fet according to claim 1, characterized in that the gate electrode (7) is polysilicon, tantalum, tungsten, tantalum nitride or titanium nitride, and has a thickness of 2-5000 nm.
  7. 7. The bulk potential optimizing structure of the thin-film silicon SOIMOSFET as claimed in claim 1, wherein the source drain region (8) is formed by ion implantation or diffusion of impurity ions, the doping type is P type or N type, the doping element is phosphorus, boron, indium or arsenic or other III-V elements, and the doping concentration is 0-1E20/cm -3 .
  8. 8. A method for preparing a bulk potential optimized structure based on a thin-film silicon soi fet as claimed in any one of claims 1-7, comprising the steps of: Providing an SOI substrate, wherein the SOI substrate comprises top silicon, a buried oxide layer and a supporting layer; forming a volume potential modulation region at the bottom of the top silicon layer by ion implantation in the top silicon layer; forming a channel region on top of the top silicon by ion implantation or diffusion in the top silicon; depositing a grid electrode material on the insulating dielectric layer, and performing anisotropic etching to form a grid electrode; And preparing a source region and a drain region on the top silicon layer through a self-aligned metal silicide forming or epitaxial process, so as to finish the structure preparation.

Description

Bulk potential optimization structure of thin silicon film SOI MOSFET and preparation method thereof Technical Field The invention relates to the technical field of semiconductor device preparation, in particular to a body potential optimization structure of a thin silicon film SOI MOSFET and a preparation method thereof. Background With the continuous development of the fields of aerospace, communication and the like, the requirements on the radiation resistance level, the performance and the like of devices are also continuously improved. Because of the advantages of small device radiation volume, small parasitic capacitance and the like, MOSFET devices based on SOI substrates are developed and applied, device processes and structural schemes are continuously increased, and the development of electronic systems in the fields is supported. At present, a MOSFET device based on an SOI substrate is mainly based on a thick silicon film or a thin silicon film, wherein the former device is large in size and parasitic capacitance, but small in body area resistance, the latter device is small in size and parasitic capacitance, good in digital-analog compatibility, but large in body area resistance, and is greatly influenced by hole charge captured by an oxygen buried layer in a radiation environment, and reliability, performance and circuit compatibility are difficult to be considered. Disclosure of Invention The invention aims to provide a body potential optimization structure of a thin-film Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a preparation method thereof, so as to solve the problems in the background technology. In order to solve the technical problems, the invention provides a bulk potential optimization structure of a thin-film silicon-on-insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which comprises top silicon, a buried oxide layer, a supporting layer, a bulk potential modulation region, a channel region, an insulating medium layer, a grid electrode and a source drain region, The top silicon layer, the buried oxide layer and the supporting layer together form an SOI substrate material; The body potential modulation area is positioned in the top silicon layer, and the bottom of the body potential modulation area is connected with the buried oxide layer; The channel region is positioned in the top layer silicon and above the body potential modulation region; the insulating medium layer is positioned above the outer part of the top silicon layer; the grid electrode is positioned on the insulating medium layer; The source/drain region is positioned in the top silicon layer and is positioned at two sides of the body potential modulation region and the channel region; The doping element type of the channel region is the same as that of the bulk potential modulation region. In one embodiment, the top silicon layer has a thickness of 1 to 500 nanometers and the buried oxide layer has a thickness of 5 to 10000 nanometers. In one embodiment, the body potential modulation region is formed by ion implantation of impurity ions, the doping type is P type or N type, the doping element is phosphorus, boron, indium or arsenic or other III-V elements, and the doping concentration is 0-1E20/cm -3. In one embodiment, the channel region is formed by ion implantation or diffusion of impurity ions, the doping type is P-type or N-type, the doping element is phosphorus, boron, indium or arsenic or other III-V elements, and the doping concentration is 0-1E20/cm -3. In one embodiment, the insulating dielectric layer is SiO 2, oxynitride, tiO 2、HfO2、Si3N4、ZrO2、Ta2O5, barium strontium titanate BST, lead zirconate titanate piezoelectric ceramic PZT or Al 2O3, and the thickness is 0.1-20 nm. In one embodiment, the gate is polysilicon, tantalum, tungsten, tantalum nitride or titanium nitride, and has a thickness of 2-5000 nm. In one embodiment, the source-drain region is formed by ion implantation or diffusion of impurity ions, the doping type is P-type or N-type, the doping element is phosphorus, boron, indium or arsenic or other III-V elements, and the doping concentration is 0-1E20/cm -3. The invention also provides a preparation method of the body potential optimization structure of the thin-film SOI MOSFET, which comprises the following steps: Providing an SOI substrate, wherein the SOI substrate comprises top silicon, a buried oxide layer and a supporting layer; forming a volume potential modulation region at the bottom of the top silicon layer by ion implantation in the top silicon layer; forming a channel region on top of the top silicon by ion implantation or diffusion in the top silicon; depositing a grid electrode material on the insulating dielectric layer, and performing anisotropic etching to form a grid electrode; And preparing a source region and a drain region on the top silicon layer through a self-aligned metal silicide forming or epitaxia