CN-122028469-A - Trench gate MOSFET structure and preparation method thereof

CN122028469ACN 122028469 ACN122028469 ACN 122028469ACN-122028469-A

Abstract

The invention provides a trench gate MOSFET structure and a preparation method thereof, wherein a buffer layer positioned in an adjacent area of a shielding layer is introduced, and a trench gate extends downwards from the upper surfaces of the buffer layer and an adjacent shielding layer into the buffer layer and the adjacent shielding layer, so that a JFET-like structure dynamically controlled by drain voltage is constructed among the buffer layer, a gate oxide layer and an epitaxial layer, the trench gate MOSFET realizes automatic adjustment of miller capacitance in a switching process, and when the drain voltage changes, the electrical state of the buffer layer is dynamically adjusted along with the change of the drain voltage, so that the device can realize both rapid switching and oscillation suppression, and lower switching loss and better switching oscillation control are realized.

Inventors

LOU QIAN

Assignees

芯迈半导体技术(杭州)股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260403

Claims (12)

1. A trench gate MOSFET structure, the trench gate MOSFET structure comprising: The semiconductor layer comprises a substrate and an epitaxial layer formed on the substrate; the shielding layers are distributed at intervals and extend downwards into the epitaxial layer from the upper surface of the epitaxial layer; A buffer layer extending downward into the epitaxial layer from the upper surface of the epitaxial layer adjacent to the shield layer, and having a vertical distance from the shield layer to the upper surface of the epitaxial layer not less than a vertical distance from the buffer layer to the upper surface of the epitaxial layer, and The trench gate structure extends downwards from the upper surfaces of the buffer layer and the shielding layer of the preset area adjacent to the buffer layer into the buffer layer and the shielding layer, and comprises a gate trench, wherein the gate trench is provided with a first bottom angle and a second bottom angle, the first bottom angle is wrapped by the shielding layer, and the second bottom angle is wrapped by the buffer layer.
2. The trench-gate MOSFET structure of claim 1 wherein a difference between a vertical distance of said shielding layer from an upper surface of said epitaxial layer and a vertical distance of said buffer layer from an upper surface of said epitaxial layer is no greater than 0.2 μm.
3. The trench-gate MOSFET structure of claim 1 further comprising a gate oxide layer formed on a bottom wall and sidewalls of the gate trench and a polysilicon layer formed on the gate oxide layer and filling the gate trench, wherein the gate trench comprises a first trench segment and a second trench segment sequentially communicating in a depth direction, the second trench segment is located below the first trench segment, a width of the second trench segment is smaller than a width of the first trench segment, the first trench segment is located above the second trench segment and the buffer layer, the first bottom corner of the second trench segment is wrapped by the shielding layer, and the second bottom corner of the second trench segment is wrapped by the buffer layer.
4. The trench-gate MOSFET structure of claim 3 wherein said gate trench has a first depth of 0.8 μm to 1.0 μm and wherein said second trench segment has a second depth of 0.4 μm to 0.5 μm.
5. The trench-gate MOSFET structure of claim 1, further comprising: The well region is positioned in the epitaxial layer between the trench gate structure and the shielding layer; A source region located on the well region; A source metal layer electrically connected with the source region; and the drain electrode metal layer is electrically connected with the substrate.
6. The trench-gate MOSFET structure of claim 5 wherein said shield layer, said buffer layer and said well region are of a first conductivity type and said source region is of a second conductivity type.
7. The trench-gate MOSFET structure of claim 1 wherein said shielding layer has a doping concentration greater than a doping concentration of said buffer layer.
8. The preparation method of the trench gate MOSFET structure is characterized by comprising the following steps of: providing a substrate, wherein an epitaxial layer is formed on the substrate; ion implantation is carried out on the preset depth of the upper surface of the epitaxial layer in the preset area, so that a plurality of buffer layers distributed at intervals are formed; performing ion implantation on the upper surface of the buffer layer at a preset position and the upper surface of the epitaxial layer adjacent to the preset position to form a plurality of shielding layers, wherein the vertical distance between the shielding layers and the upper surface of the epitaxial layer is not smaller than the vertical distance between the buffer layer and the upper surface of the epitaxial layer; The trench gate structure comprises a gate trench, wherein the gate trench is provided with a first base angle and a second base angle, the first base angle is wrapped by the shielding layer, and the second base angle is wrapped by the buffering layer.
9. The method of claim 8, wherein the step of forming the trench-gate structure by extending a predetermined depth downward from the buffer layer and the upper surface of the shield layer in a predetermined region adjacent to the buffer layer comprises: etching the buffer layer and the shielding layer of a preset area adjacent to the buffer layer to form the grid groove; forming a gate oxide layer on the bottom wall and the side wall of the gate trench; And forming a polysilicon layer filling the gate trench on the gate oxide layer.
10. The method of fabricating a trench-gate MOSFET structure of claim 9, wherein forming said gate trench comprises: etching the buffer layer and the shielding layer of a preset area adjacent to the buffer layer to form a first groove section; Etching the first groove section near the bottom of the shielding layer to form a second groove section, wherein the width of the second groove section is smaller than that of the first groove section, so that the first bottom angle of the second groove section is wrapped by the shielding layer, the second bottom angle of the second groove section is wrapped by the buffer layer, and the first groove section and the second groove section jointly form the grid groove.
11. The method of fabricating a trench-gate MOSFET structure of claim 8, further comprising: ion implantation is carried out on the preset depth of the upper surface of the epitaxial layer between the trench gate structure and the shielding layer to form a well region; ion implantation is carried out on the preset depth of the upper surface of the well region to form a source region; Forming a source metal layer electrically connected with the source region; a drain metal layer is formed in electrical connection with the substrate.
12. The method of manufacturing a trench-gate MOSFET structure as set forth in claim 11, wherein said shielding layer, said buffer layer and said well region are of a first conductivity type and said source region is of a second conductivity type.

Description

Trench gate MOSFET structure and preparation method thereof Technical Field The invention relates to the technical field of semiconductor device manufacturing, in particular to a trench gate MOSFET structure and a manufacturing method thereof. Background In recent years, silicon carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been widely accepted in the fields of high-frequency and high-efficiency power electronics applications such as new energy automobiles, charging piles, photovoltaic inversion, and the like, due to their excellent material characteristics. Compared with a silicon-based Insulated Gate Bipolar Transistor (IGBT) with the same voltage withstand level and specific on resistance, the area of the SiC MOSFET chip can be reduced by 65 times theoretically, the SiC MOSFET chip has lower Miller capacitance (Cgd), and the switching speed and the working frequency of the device can be remarkably improved, so that the volume and the weight of a power electronic device are greatly reduced, and a system is promoted to develop in the high-efficiency and light-weight directions. The trench gate SiC MOSFET further reduces the specific on-resistance of the device by realizing higher channel density, and becomes an important development direction in the field. However, under high frequency operating conditions, due to the interaction of the high switching speed of the SiC MOSFET with stray inductances in the power electronics system, serious switching oscillations can occur, resulting in problems of current and voltage overshoots, additional power losses, device false turn-on, and the like, and even direct damage to the device may be possible. To suppress switching oscillations, the prior art generally employs increasing gate resistance or increasing miller capacitance to reduce switching speed, such as by increasing gate oxide thickness or adjusting Current Spreading Layer (CSL) concentration to increase miller capacitance, thereby reducing voltage change rate (dV/dt). However, although these approaches mitigate switching oscillations to some extent, the inevitable increase in switching losses limits the advantages of SiC MOSFETs in high frequency applications. Thus, the prior art solutions have difficulty in achieving co-optimization of low switching oscillations, low switching losses and high reliability at the same time. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a trench gate MOSFET structure and a method for manufacturing the same, which are used for solving the problem that the switching loss and the switching oscillation cannot be cooperatively optimized in the prior art. To achieve the above and other related objects, the present invention provides a trench gate MOSFET structure comprising: The semiconductor layer comprises a substrate and an epitaxial layer formed on the substrate; the shielding layers are distributed at intervals and extend downwards into the epitaxial layer from the upper surface of the epitaxial layer; A buffer layer extending downward into the epitaxial layer from the upper surface of the epitaxial layer adjacent to the shield layer, and having a vertical distance from the shield layer to the upper surface of the epitaxial layer not less than a vertical distance from the buffer layer to the upper surface of the epitaxial layer, and The trench gate structure extends downwards from the upper surfaces of the buffer layer and the shielding layer of the preset area adjacent to the buffer layer into the buffer layer and the shielding layer, and comprises a gate trench, wherein the gate trench is provided with a first bottom angle and a second bottom angle, the first bottom angle is wrapped by the shielding layer, and the second bottom angle is wrapped by the buffer layer. Optionally, a difference between a vertical distance of the shielding layer from the upper surface of the epitaxial layer and a vertical distance of the buffer layer from the upper surface of the epitaxial layer is not greater than 0.2 μm. Optionally, the trench gate further comprises a gate oxide layer formed on the bottom wall and the side wall of the gate trench and a polysilicon layer formed on the gate oxide layer and filled with the gate trench, wherein the gate trench comprises a first trench section and a second trench section which are sequentially communicated in the depth direction, the second trench section is positioned below the first trench section, the width of the second trench section is smaller than that of the first trench section, the first trench section is positioned above the second trench section and the buffer layer, the first bottom angle of the second trench section is wrapped by the shielding layer, and the second bottom angle of the second trench section is wrapped by the buffer layer. Further, the gate trench has a first depth of 0.8 μm to 1.0 μm, wherein the seco