CN-122028470-A - Planar gate MOSFET structure and preparation method thereof

CN122028470ACN 122028470 ACN122028470 ACN 122028470ACN-122028470-A

Abstract

The invention provides a planar gate MOSFET structure and a preparation method thereof, wherein ion implantation is carried out on the upper surface of an epitaxial layer between well regions to form a buffer layer, the buffer layer comprises a plurality of buffer layer units which are distributed at intervals along the length direction of the well regions, each buffer layer unit is at least in contact connection with the well region positioned at one side of the buffer layer, thus a JFET structure controlled by drain voltage is formed when a device works, the self-adaptive adjustment of Miller capacitance is realized, and in addition, the buffer layer further shares the electric field shielding function of a gate oxide layer to relieve the electric field concentration effect of the gate oxide layer.

Inventors

LOU QIAN

Assignees

芯迈半导体技术(杭州)股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260403

Claims (12)

1. The preparation method of the planar gate MOSFET structure is characterized by comprising the following steps of: S1, providing a substrate, wherein an epitaxial layer is formed on the substrate; s2, carrying out ion implantation on the preset depth of the upper surface of the epitaxial layer to form a plurality of strip-shaped well regions; S3, performing ion implantation on the preset depth of the upper surface of the well region to form a plurality of strip-shaped source regions; s4, carrying out ion implantation on the preset depth of the upper surface of the epitaxial layer between two adjacent well regions to form a buffer layer, wherein the buffer layer comprises a plurality of buffer layer units which are distributed at intervals along the length direction of the well regions, and each buffer layer unit is at least in contact connection with the well region positioned at one side of the buffer layer.
2. The method of manufacturing a planar gate MOSFET structure according to claim 1, wherein in step S2, ion implantation is performed to a predetermined depth on an upper surface of the epitaxial layer to form a plurality of strip-shaped well regions, and in step S3, ion implantation is performed to a predetermined depth on an upper surface of the well region to form a plurality of strip-shaped source regions, comprising: forming a patterned well region hard mask layer on the epitaxial layer; performing ion implantation to a preset depth on the upper surface of the epitaxial layer based on the patterned well region hard mask layer to form a plurality of strip-shaped well regions; Forming a side wall on the side wall of the patterned well region hard mask layer, and forming a patterned source region hard mask layer on the well region; and performing ion implantation to a preset depth on the upper surface of the well region based on the patterned well region hard mask layer and the patterned source region hard mask layer which form the side wall to form a plurality of strip-shaped source regions.
3. A planar gate MOSFET structure is characterized in that the planar gate MOSFET structure comprises: A substrate and an epitaxial layer formed on the substrate; a plurality of strip-shaped well regions extending downwards from the upper surface of the epitaxial layer into the epitaxial layer; A plurality of strip-shaped source regions extending downwards from the upper surface of the well region into the well region, and The buffer layer extends downwards into the epitaxial layer from the upper surface of the epitaxial layer between two adjacent well regions, the buffer layer comprises a plurality of buffer layer units which are arranged at intervals along the length direction of the well regions, and each buffer layer unit is at least in contact connection with the well region positioned at one side of the buffer layer.
4. The planar gate MOSFET structure of claim 3, wherein said well region and said buffer layer are of a first conductivity type and said source region is of a second conductivity type.
5. The planar gate MOSFET structure of claim 3, wherein all of said buffer layer cells are in contact with said well regions on opposite sides of said buffer layer.
6. The planar gate MOSFET structure of claim 5, wherein the buffer layer unit has a projected shape in a horizontal direction comprising a rectangle or a "cross".
7. The planar gate MOSFET structure of claim 5, wherein said buffer layer further comprises a connection portion connecting said buffer layer cells along a length direction of said well region.
8. The planar gate MOSFET structure of claim 3 wherein said buffer layer units comprise first buffer layer units and second buffer layer units alternately arranged along a length direction of said well region, wherein said first buffer layer units are in contact connection with said well region on one side of said buffer layer, and in said alternate arrangement direction, said first buffer layer units are alternately in contact connection with said well regions on opposite sides, and said second buffer layer units are in contact connection with said well regions on both sides of said buffer layer.
9. The planar gate MOSFET structure of claim 3 wherein all buffer layer units are in contact with said well region on one side of said buffer layer, and adjacent two of said buffer layer units are in contact with said well regions on opposite sides, respectively.
10. The planar gate MOSFET structure of claim 3, wherein the buffer layer has a thickness of 0.3 μm to 0.6 μm.
11. The planar gate MOSFET structure of claim 3, wherein the buffer layer has an ion doping concentration of 1e16cm -3 ~1e17cm -3 .
12. The planar gate MOSFET structure of claim 3, the planar gate MOSFET structure is characterized by further comprising: The gate oxide layer is formed on the epitaxial layer and the buffer layer between the adjacent well regions and extends to partial areas of the source regions at two sides; and the polycrystalline silicon layer is formed on the gate oxide layer.

Description

Planar gate MOSFET structure and preparation method thereof Technical Field The invention relates to the technical field of semiconductor device manufacturing, in particular to a planar gate MOSFET structure and a manufacturing method thereof. Background Silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) are widely used in the field of power electronics due to their excellent properties of wide bandgap semiconductor materials. Compared with a silicon-based Insulated Gate Bipolar Transistor (IGBT) with the same voltage withstand level and specific on resistance, the area of the SiC MOSFET chip can be reduced by about 65 times theoretically, so that the SiC MOSFET chip has lower Miller capacitance, the switching speed and the working frequency of a device can be remarkably improved, the volume and the weight of a power electronic device are greatly reduced, and a power electronic system is promoted to develop in the high-efficiency and light-weight directions. Currently, the most mature planar gate SiC MOSFETs are moving towards finer cell sizes, i.e. the cell size is continually reduced, and the most advanced processes have achieved cell sizes of about 3 microns. However, this refined cell design also brings new technical problems. Firstly, under high frequency working conditions, due to the interaction of the high switching speed of the SiC MOSFET and stray inductance in a power electronic system, serious switching oscillation can be generated, so that problems of current and voltage overshoot, additional power loss increase, false start and the like are caused, and even devices can be directly damaged in serious cases. In order to solve the switching oscillation problem, the switching speed is usually reduced by increasing the gate resistance or increasing the miller capacitance in practical application, but this inevitably increases the switching loss, and limits the exertion of the advantages of SiC MOSFETs in the high frequency domain. Therefore, the prior art solutions have difficulty in achieving co-optimization of low switching oscillations, low switching losses and high short-circuit reliability at the same time. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a planar gate MOSFET structure and a method for manufacturing the same, which are used for solving the problem that the switching loss and the switching oscillation cannot be cooperatively optimized in the prior art. To achieve the above and other related objects, the present invention provides a method for manufacturing a planar gate MOSFET structure, including: S1, providing a substrate, wherein an epitaxial layer is formed on the substrate; s2, carrying out ion implantation on the preset depth of the upper surface of the epitaxial layer to form a plurality of strip-shaped well regions; S3, performing ion implantation on the preset depth of the upper surface of the well region to form a plurality of strip-shaped source regions; s4, carrying out ion implantation on the preset depth of the upper surface of the epitaxial layer between two adjacent well regions to form a buffer layer, wherein the buffer layer comprises a plurality of buffer layer units which are distributed at intervals along the length direction of the well regions, and each buffer layer unit is at least in contact connection with the well region positioned at one side of the buffer layer. Optionally, in step S2, ion implantation is performed to a preset depth on the upper surface of the epitaxial layer to form a plurality of strip-shaped well regions, and in step S3, the method for performing ion implantation to a preset depth on the upper surface of the well region to form a plurality of strip-shaped source regions includes: forming a patterned well region hard mask layer on the epitaxial layer; performing ion implantation to a preset depth on the upper surface of the epitaxial layer based on the patterned well region hard mask layer to form a plurality of strip-shaped well regions; Forming a side wall on the side wall of the patterned well region hard mask layer, and forming a patterned source region hard mask layer on the well region; and performing ion implantation to a preset depth on the upper surface of the well region based on the patterned well region hard mask layer and the patterned source region hard mask layer which form the side wall to form a plurality of strip-shaped source regions. The present invention also provides a planar gate MOSFET structure comprising: A substrate and an epitaxial layer formed on the substrate; a plurality of strip-shaped well regions extending downwards from the upper surface of the epitaxial layer into the epitaxial layer; A plurality of strip-shaped source regions extending downwards from the upper surface of the well region into the well region, and The buffer layer extends downwards into the epitaxial layer from the upp