CN-122028471-A - LDMOS device and manufacturing method thereof

CN122028471ACN 122028471 ACN122028471 ACN 122028471ACN-122028471-A

Abstract

The invention relates to an LDMOS device and a manufacturing method thereof, wherein the LDMOS device comprises a drift region, a first Metal Oxide Semiconductor (MOS) and a second Metal Oxide Semiconductor (MOS) and a first Metal Oxide Semiconductor (MOS); the semiconductor device comprises a drift region, a drain region, a source extraction region, a first conductivity type well region, a drain extraction region and a gate, wherein the drift region is arranged in the semiconductor device, the second conductivity type is arranged in the drift region, the first conductivity type doped region is arranged in the drift region and above the drift region, the doping concentration of the first conductivity type doped region is larger than that of the drift region, the body region is provided with the second conductivity type, the source extraction region is provided with the first conductivity type and is arranged in the body region, the first conductivity type doped region is arranged between the first conductivity type well region and the body region, and the drain extraction region is provided with the first conductivity type and is arranged in the first conductivity type well region. The first conductive type doped region can reduce the on-resistance of the device. The depletion region of the device at the time of withstand voltage can assist in depleting majority carriers above and below, and thus has a higher withstand voltage.

Inventors

WANG HAO
ZHANG ZIAO
WANG TING
HE NAILONG

Assignees

无锡华润上华科技有限公司

Dates

Publication Date: 20260512
Application Date: 20241111

Claims (10)

1. An LDMOS device, comprising: A drift region having a first conductivity type; A depletion region in the drift region having a second conductivity type, the first and second conductivity types being opposite conductivity types; A first conductivity type doped region located in the drift region above the depletion region, the doping concentration of the first conductivity type doped region being greater than the doping concentration of the drift region; A body region having a second conductivity type; a source extraction region having a first conductivity type located in the body region; a first conductivity type well region, the first conductivity type doped region being located between the first conductivity type well region and the body region; a drain-out region having a first conductivity type, located in the first conductivity type well region; And a gate.
2. The LDMOS device of claim 1, further comprising a field oxide layer at least partially over the drift region, the gate extending from a location proximate the body region onto the field oxide layer; The field oxide layer is provided with a plurality of injection windows, the first conductive type doped region comprises injection regions corresponding to the injection windows one by one, each injection region is formed by ion injection through the corresponding injection window, and each injection window is positioned between the grid electrode and the first conductive type well region.
3. The LDMOS device of claim 1, wherein the well region of the first conductivity type is located in the drift region, and/or The bottom of the first conductivity type doped region is separated from the depletion region by a portion of the structure of the drift region, the bottom of the depletion region being above the bottom of the drift region.
4. The LDMOS device of claim 1, further comprising a substrate, the drift region being at least partially on the substrate, the body region being in the substrate, the body region and the drift region being separated by the substrate.
5. The LDMOS device of claim 1, wherein a doping concentration of the drain lead-out region is greater than a doping concentration of the first conductivity type well region.
6. The LDMOS device of claim 1, wherein the depletion region is located between a side of the body region adjacent to the first conductivity type well region and a side of the first conductivity type well region adjacent to the body region.
7. A manufacturing method of an LDMOS device comprises the following steps: the method comprises the steps of obtaining a wafer formed with a drift region, a body region, a source extraction region, a first conduction type well region, a drain extraction region and a grid electrode, wherein the drift region is provided with a first conduction type, the body region is provided with a second conduction type, the source extraction region is provided with the first conduction type and is formed in the body region, and the drain extraction region is provided with the first conduction type and is formed in the first conduction type well region; The manufacturing method of the LDMOS device is characterized by further comprising the step of forming a depletion region of a second conductivity type in the drift region and the step of forming a doped region of a first conductivity type in the drift region, wherein the doped region of the first conductivity type is positioned above the depletion region and between the well region of the first conductivity type and the body region, and the doping concentration of the doped region of the first conductivity type is larger than that of the drift region.
8. The method of manufacturing an LDMOS device of claim 7, comprising: Forming the depletion region in the drift region; Forming a patterned oxide layer on a first main surface of a wafer, wherein the oxide layer comprises a field oxide layer at least partially formed on the drift region; forming the grid electrode, wherein one side of the grid electrode extends to the field oxide layer; Forming the body region and the first conductivity type well region; forming the source lead-out region in the body region and forming the drain lead-out region in the first conductivity type well region; patterning the field oxide layer to form a plurality of implantation windows between the gate and the first conductivity type well region; And forming implantation regions corresponding to the implantation windows one by one in the drift region below the implantation windows by ion implantation, wherein the first conductive type doping regions consist of the implantation regions.
9. The method of manufacturing an LDMOS device according to claim 8, wherein the step of forming the depletion region in the drift region is to implant ions of a second conductivity type by a high energy ion implantation process to form the depletion region.
10. The method of manufacturing an LDMOS device of claim 7, comprising: Forming a patterned oxide layer on a first main surface of a wafer, wherein the oxide layer comprises a field oxide layer at least partially formed on the drift region; forming the grid electrode, wherein one side of the grid electrode extends to the field oxide layer; Forming the body region and the first conductivity type well region; forming the source lead-out region in the body region and forming the drain lead-out region in the first conductivity type well region; patterning the field oxide layer to form a plurality of implantation windows between the gate and the first conductivity type well region; And respectively injecting first conductive type ions and second conductive type ions into the drift region through each injection window, forming a plurality of injection regions and depletion regions below each injection region in the drift region, wherein each injection region comprises a first conductive type doping region.

Description

LDMOS device and manufacturing method thereof Technical Field The invention relates to the field of semiconductor manufacturing, in particular to an LDMOS device and a manufacturing method of the LDMOS device. Background As a core device in BCD (Bipolar-CMOS-DMOS) technology, LDMOS (laterally diffused metal oxide semiconductor field effect transistor) are generally required to have low on-resistance (Rdson) and high breakdown voltage (i.e., BV). However, in the LDMOS structure, rdson and BV are often in a state where fish and bear feet cannot be used together, that is, on-resistance is reduced to lower the withstand voltage, and on-resistance is increased to raise the withstand voltage. Disclosure of Invention Accordingly, it is necessary to provide an LDMOS device and a method for manufacturing the same that can achieve a compatible device withstand voltage while reducing the on-resistance of the device. An LDMOS device comprises a drift region, a depletion region, a first conduction type well region, a drain extraction region and a grid, wherein the drift region is provided with a first conduction type, the depletion region is located in the drift region and is provided with a second conduction type, the first conduction type and the second conduction type are opposite in conduction type, a first conduction type doping region is located in the drift region and above the depletion region, the doping concentration of the first conduction type doping region is larger than that of the drift region, the body region is provided with a second conduction type, the source extraction region is provided with a first conduction type and is located in the body region, the first conduction type well region is located between the first conduction type well region and the body region, the drain extraction region is provided with a first conduction type and is located in the first conduction type well region, and the grid is provided with a first conduction type. In the LDMOS device, the first conductive type doped region with the concentration larger than that of the drift region is formed in the drift region, so that majority carriers are introduced, and the on-resistance of the device can be reduced. And by providing a depletion region of the second conductivity type (minority carrier) below the first conductivity type doped region in the drift region, the depletion region of the device can assist in depleting the majority carrier above and below when the device is voltage tolerant, so the device has a higher voltage tolerant. In one embodiment, the LDMOS device further comprises a field oxide layer, wherein the field oxide layer is at least partially arranged on the drift region, the grid electrode extends from a position close to the body region to the field oxide layer, a plurality of injection windows are formed in the field oxide layer, the first conductive type doped regions comprise injection regions in one-to-one correspondence with the injection windows, each injection region is formed by ion injection through the corresponding injection window, and each injection window is arranged between the grid electrode and the first conductive type well region. In one embodiment, the first conductivity type well region is located in the drift region. In one embodiment, the bottom of the first conductivity type doped region is separated from the depletion region by a portion of the structure of the drift region, the bottom of the depletion region being above the bottom of the drift region. In one embodiment, the LDMOS device further comprises a substrate, the drift region being at least partially located on the substrate, the body region being located in the substrate, the body region and the drift region being separated by the substrate. In one embodiment, the drain lead-out region has a doping concentration greater than that of the first conductivity type well region. In one embodiment, the depletion region is located between a side of the body region adjacent to the first conductivity type well region and a side of the first conductivity type well region adjacent to the body region. A manufacturing method of an LDMOS device comprises the following steps: the method comprises the steps of obtaining a wafer formed with a drift region, a body region, a source extraction region, a first conduction type well region, a drain extraction region and a grid electrode, wherein the drift region is provided with a first conduction type, the body region is provided with a second conduction type, the source extraction region is provided with the first conduction type and is formed in the body region, and the drain extraction region is provided with the first conduction type and is formed in the first conduction type well region; The manufacturing method of the LDMOS device further comprises the steps of forming a depletion region of a second conductivity type in the drift region and forming a doped region of a first conductivity typ