CN-122028472-A - Fin gate structure LDMOS device and manufacturing method thereof

Abstract

The invention provides a fin gate structure LDMOS device and a manufacturing method thereof. The device comprises a semiconductor substrate, an isolation structure, a drift region, a well region, a source region, a drain region and a body contact region, wherein the semiconductor substrate is provided with a buried layer and an epitaxial layer. The device is provided with a groove extending along the width direction of the device in the active region, a grid structure covers the surface of the active region and fills the groove, and a fin-type grid is formed at the groove. The structure enables a conductive channel to be formed on the upper surface of the active region and on the side wall and the bottom surface of the groove when the device is conducted. According to the invention, the groove structure is introduced in the width direction of the device, so that the effective channel width in unit area is increased, and on-resistance is obviously reduced on the premise of not increasing the layout area of the device.

Inventors

• TIAN YE
• LU GUANGYUAN
• CHEN YONG
• WANG LI
• CHEN HUALUN

Assignees

• 华虹半导体制造(无锡)有限公司
• 华虹半导体(无锡)有限公司
• 上海华虹宏力半导体制造有限公司

Dates

Publication Date

20260512

Application Date

20260116

Claims (17)

1. 1. A fin gate structure LDMOS device, comprising: a semiconductor substrate having a buried layer and an epitaxial layer on the buried layer; The isolation structure is arranged in the epitaxial layer and defines an active region; the first conduction type drift region, the first conduction type well region and the second conduction type well region are positioned in the epitaxial layer; the source electrode region, the drain electrode region and the body contact region are arranged on the surface layer of the epitaxial layer; A trench located in the active region and extending in a device width direction; The grid electrode structure comprises a grid dielectric layer and a grid electrode conducting layer, wherein the grid electrode conducting layer covers part of the surface of the active region and fills the groove; And the grid structure forms a fin grid at the groove, so that a conductive channel is formed on the upper surface of the active region and the side wall and the bottom surface of the groove when the LDMOS device is conducted.
2. 2. The fin gate structure LDMOS device of claim 1, wherein said isolation structure is a shallow trench isolation structure.
3. 3. The fin gate structure LDMOS device of claim 1, further comprising a high-voltage gate dielectric structure disposed on a surface of said first conductivity type drift region.
4. 4. The fin-gate structure LDMOS device of claim 3, wherein said high-voltage gate dielectric structure is further filled in said trench within said first conductivity type drift region.
5. 5. The fin-gate structure LDMOS device of claim 3, wherein said first portion of said gate conductive layer is located on said gate dielectric layer and said second portion of said gate conductive layer extends to a surface of said high-voltage gate dielectric structure.
6. 6. The fin-gate structure LDMOS device of claim 1, further comprising a bottom impurity region within said epitaxial layer and below said drift region of the first conductivity type, said bottom impurity region having a second conductivity type.
7. 7. The fin-gate structure LDMOS device of claim 1, wherein said buried layer is a doped layer of a first conductivity type and said epitaxial layer is a doped layer of a second conductivity type.
8. 8. The fin-gate structure LDMOS device of claim 1, wherein said first conductivity type is N-type and said second conductivity type is P-type.
9. 9. The fin-gate structure LDMOS device of claim 1, wherein said source region and said drain region are heavily doped regions of a first conductivity type and said body contact region is a heavily doped region of a second conductivity type.
10. 10. The manufacturing method of the fin gate structure LDMOS device is characterized by comprising the following steps of: step one, providing a semiconductor substrate, forming a buried layer on the semiconductor substrate, and growing an epitaxial layer on the buried layer; Step two, forming an isolation structure in the epitaxial layer, wherein the isolation structure defines an active region; Forming a groove extending along the width direction of the device in the active region; forming a first conduction type drift region, a first conduction type well region and a second conduction type well region in the epitaxial layer, and forming a high-voltage gate dielectric structure; forming a gate dielectric layer on the surface of the active region and the inner wall of the groove, and forming a gate conducting layer on the gate dielectric layer, wherein the gate conducting layer fills the groove; And step six, forming a source region and a body contact region in the second conductivity type well region, and forming a drain region in the first conductivity type drift region.
11. 11. The method of manufacturing a fin-gate structure LDMOS device according to claim 10, wherein in step three, said forming a trench extending in a width direction of the device is performed by defining a trench pattern by a photolithography process and etching said epitaxial layer by an etching process.
12. 12. The method of manufacturing a fin gate structure LDMOS device according to claim 10, wherein in step four, said step of forming a high voltage gate dielectric structure comprises depositing a dielectric material, removing said dielectric material on the surface of said second conductivity type well region by using photolithography and etching processes, and retaining said dielectric material on the surface of said first conductivity type drift region as said high voltage gate dielectric structure.
13. 13. The method of manufacturing a fin gate structure LDMOS device of claim 10, further comprising forming a bottom impurity region under said first conductivity type drift region and having a second conductivity type in step four.
14. 14. The method of manufacturing a fin-gate structure LDMOS device according to claim 13, wherein in step four, said bottom impurity region is formed by an ion implantation process, and said bottom impurity region and said first conductivity type drift region are defined by sharing the same photolithographic mask.
15. 15. The method of manufacturing a fin-gate structure LDMOS device of claim 10, wherein in step four, said forming a well region of a first conductivity type and said well region of a second conductivity type is performed after forming said drift region of the first conductivity type.
16. 16. The method of manufacturing a fin-gate LDMOS device according to claim 10, wherein in step one, said buried layer is a doped layer of a first conductivity type and said epitaxial layer is a doped layer of a second conductivity type.
17. 17. The method of manufacturing a fin-gate structure LDMOS device of claim 10, wherein in step four, said first conductivity type is N-type and said second conductivity type is P-type.

Description

Fin gate structure LDMOS device and manufacturing method thereof Technical Field The invention relates to the field of integrated circuit manufacturing, in particular to a fin gate structure LDMOS device and a manufacturing method thereof. Background The Lateral Double-diffused metal oxide semiconductor (LDMOS) device has the advantages of high input impedance, high switching speed, good thermal stability and the like, and is widely applied to power integrated circuits and is a core component in a bipolar-CMOS-DMOS (BCD) process. The design and fabrication of LDMOS devices face a compromise between core performance metrics, the most critical of which is the contradiction between breakdown voltage (BV, breakdown Voltage) and On-resistance (Ron). Typically, the on-resistance of an LDMOS is inversely related to its source-drain breakdown voltage, a so-called "silicon-limited" constraint. On the premise of ensuring that the breakdown voltage of the LDMOS meets the design requirement, obtaining a sufficiently small on-resistance is a key for improving the efficiency of the power device and reducing the power consumption. As shown in fig. 1, a schematic perspective view of an existing LDMOS device with a typical planar gate structure is shown. The device is provided with a Source (Source), a P-type well (PW), a Gate (Gate), a high-voltage Gate oxide (HVGO), an N-type drift region (Ndrift) and a Drain (Drain) in sequence along a channel direction on a semiconductor substrate. In operation, current flows from the source, through the inversion layer channel at the surface of the P-well, through the drift region to the drain. In the structure shown in fig. 1, the Gate (Gate) of the device is tiled with the surface of the active region, and the channel is formed only on the two-dimensional planar interface of the P-well (PW) in contact with the Gate oxide. This conventional planar structure has significant limitations: The effective channel Width is limited-as shown in the Width direction indicated in fig. 1, the effective channel Width of the device is directly dependent on the physical Width of the device on the layout. This means that to increase the effective channel Width to increase the on-current and decrease the on-resistance (Ron), the physical size of the device in the Width direction must be linearly increased. Area utilization is low because the on-current is dependent only on the surface channel and the volume within the semiconductor material is not used to transport current, resulting in a lower current density per chip area. In summary, on the premise of ensuring the layout size of the LDMOS device (i.e., not increasing the chip area) and keeping the breakdown voltage index unchanged, it is difficult to further reduce the specific on-resistance (Rsp) of the planar gate structure in the prior art. Therefore, a new device structure design is needed, and the effective channel width is increased by using the three-dimensional structure by breaking through the limitation of the planar channel, so that the device performance is remarkably improved. Disclosure of Invention The technical problem to be solved by the application is that the conventional planar gate structure LDMOS device is limited by the channel width of a two-dimensional plane, and on the premise that the layout area of the device is not increased and the breakdown voltage is kept unchanged, the on-resistance and the specific on-resistance of the device are difficult to further reduce. In order to solve the technical problems, the present application provides a fin gate structure LDMOS device, which includes: a semiconductor substrate having a buried layer and an epitaxial layer on the buried layer; The isolation structure is arranged in the epitaxial layer and defines an active region; the first conduction type drift region, the first conduction type well region and the second conduction type well region are positioned in the epitaxial layer; the source electrode region, the drain electrode region and the body contact region are arranged on the surface layer of the epitaxial layer; A trench located in the active region and extending in a device width direction; The grid structure comprises a grid dielectric layer and a grid conductive layer; The grid electrode conductive layer covers part of the surface of the active region and fills the groove; And the grid structure forms a fin grid at the groove, so that a conductive channel is formed on the upper surface of the active region and the side wall and the bottom surface of the groove when the LDMOS device is conducted. Preferably, the isolation structure is a shallow trench isolation structure. Preferably, the LDMOS device further comprises a high-voltage gate dielectric structure, and the high-voltage gate dielectric structure is arranged on the surface of the first conductivity type drift region. Preferably, the high-voltage gate dielectric structure is further filled in the trench located i