CN-122028473-A - Semiconductor structure

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate, a first doping type epitaxial layer, at least one gate structure, a plurality of second doping type epitaxial layers, a plurality of doping regions and a plurality of source regions. The first doping type epitaxial layer is arranged on the substrate. The at least one gate structure is disposed on the first doping type epitaxial layer and extends in a first direction. The second doping type epitaxial layer is arranged on two sides of the gate structure and the first doping type epitaxial layer, wherein the bottom of at least one gate structure is lower than the bottom of the second doping type epitaxial layer. The doped regions are arranged at intervals in the first direction and cover a plurality of bottom corners at two sides of the grid structure. The source regions are disposed on both sides of the at least one gate structure and the second doping type epitaxial layer. The semiconductor structure may at least encapsulate an electrical breakdown of the gate structure at high voltages.

Inventors

• TANG SONGNIAN
• Chen hetai
• XU XIUWEN

Assignees

• 尼克森微电子股份有限公司
• 帅群微电子股份有限公司

Dates

Publication Date

20260512

Application Date

20241112

Claims (9)

1. 1. A semiconductor structure, comprising: A first doping type epitaxial layer arranged on a substrate; At least one gate structure disposed on the first doping type epitaxial layer and extending in a first direction; A plurality of second doping type epitaxial layers arranged on two sides of the at least one gate structure and the first doping type epitaxial layers, wherein a bottom of the at least one gate structure is lower than a bottom of the plurality of second doping type epitaxial layers; multiple doped regions spaced apart in the first direction and surrounding multiple bottom corners of the at least one gate structure, and And the source regions are arranged on two sides of the at least one gate structure and the second doping type epitaxial layers.
2. 2. The semiconductor structure of claim 1, wherein the plurality of doped regions and the plurality of second doping type epitaxial layers are of a same doping type, a doping concentration of the plurality of doped regions being greater than a doping concentration of the plurality of second doping type epitaxial layers.
3. 3. The semiconductor structure of claim 1, wherein the at least one gate structure comprises a first gate structure and a second gate structure, and the first gate structure and the second gate structure are separated by one of the second doping type epitaxial layers and are aligned in parallel in a second direction perpendicular to the first direction.
4. 4. The semiconductor structure of claim 3, wherein the plurality of doped regions comprises: a plurality of first left doped regions surrounding the bottom corners of the left side of the first gate structure, and The first right doped regions cover the bottom corners of the right side of the first gate structure, and the first left doped regions and the first right doped regions are symmetrically arranged with a first central axis of the first gate structure, and the first central axis is parallel to the first direction.
5. 5. The semiconductor structure of claim 4, wherein a spacing between any two adjacent doped regions of the plurality of doped regions spaced apart in parallel to the first direction is between 0.5 microns and 2 microns.
6. 6. The semiconductor structure of claim 3, wherein the plurality of doped regions comprises: a plurality of first left doped regions surrounding the bottom corners of the left side of the first gate structure, and The first right doped regions wrap the bottom corners of the right side of the first gate structure, and the first left doped regions and the first right doped regions are staggered in the second direction.
7. 7. The semiconductor structure of claim 6, wherein a spacing between any two adjacent doped regions is 1 micron to 4 microns between the plurality of doped regions spaced apart in parallel with the first direction.
8. 8. The semiconductor structure of claim 6, wherein the plurality of doped regions comprises: a plurality of second left doped regions surrounding the bottom corners of the left side of the second gate structure, and The second right doped regions cover the bottom corners of the right side of the second gate structure, the second left doped regions and the second right doped regions are arranged in a staggered manner in the second direction, the second left doped regions and the first right doped regions are symmetrically arranged by taking a central line between the first gate structure and the second gate structure as an axis, and the second right doped regions and the first left doped regions are symmetrically arranged by taking the central line as an axis.
9. 9. The semiconductor structure of claim 6, wherein the plurality of doped regions comprises: a plurality of second left doped regions surrounding the bottom corners of the left side of the second gate structure, and The second right doped regions wrap the bottom corners of the right side of the second grid structure, the second left doped regions and the second right doped regions are arranged in a staggered mode in the second direction, the second left doped regions and the first right doped regions are arranged in a staggered mode in the second direction, and the second right doped regions and the first left doped regions are arranged in a staggered mode in the second direction.

Description

Semiconductor structure Technical Field The present disclosure relates to a semiconductor structure. Background Compared with the conventional planar MOS device, the current trend is along the plane on the surface of the substrate, and the trench-Oxide-Semiconductor (MOS) device has a gate disposed in the trench, so that the channel position of the MOS device is changed, and the current trend of the MOS device is perpendicular to the substrate. Therefore, the size of the device can be reduced, the aggressiveness of the device is improved, and the manufacturing cost is reduced. Common Metal-Oxide-semiconductor devices include Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), insulated gate diode (Insulated Gate Bipolar Transistor, IGBT), and the like. While cost can be reduced by shrinking device geometry, various tradeoffs and challenges must be met when increasing device functionality per unit area. For example, decreasing the area ratio on-state resistance R on xA may have an effect on other electrical device characteristics, such as device reliability that may be limited by high electric fields in the trench dielectric (e.g., gate oxide). In view of the foregoing, it is desirable to provide a trench metal oxide semiconductor device that has improved electrical characteristics. Disclosure of Invention The present disclosure provides a semiconductor structure including a substrate, a first doping type epitaxial layer, at least one gate structure, a plurality of second doping type epitaxial layers, a plurality of doping regions, and a plurality of source/drain regions. The first doping type epitaxial layer is arranged on the substrate. The at least one gate structure is disposed on the first doping type epitaxial layer and extends in a first direction. The second doping type epitaxial layers are arranged on two sides of the at least one gate structure and the first doping type epitaxial layers, wherein the bottom of the at least one gate structure is lower than the bottom of the second doping type epitaxial layers. The doped regions are arranged at intervals in the first direction and cover a plurality of bottom corners at two sides of the grid structure. The source region is disposed on both sides of the at least one gate structure and the second doping type epitaxial layer. In some embodiments, the doped region and the second doping type epitaxial layer are of the same doping type, and the doping concentration of the doped region is greater than the doping concentration of the second doping type epitaxial layer. In some embodiments, the at least one gate structure includes a first gate structure and a second gate structure, and the first gate structure is isolated from the second gate structure by one of the second doping type epitaxial layers and arranged in parallel in a second direction perpendicular to the first direction. In some embodiments, the doped regions include a plurality of first left doped regions and a plurality of first right doped regions. A plurality of first left doped regions wrap around the bottom corner of the left side of the first gate structure. The bottom corners of the right side of the first grid structure are covered by the plurality of first right side doped regions, and the first left side doped regions and the first right side doped regions are symmetrically arranged with a first central axis of the first grid structure, wherein the first central axis is parallel to the first direction. In some embodiments, the doped regions are spaced apart in a parallel first direction, with a spacing between any adjacent two doped regions of 0.5 microns to 2 microns. In some embodiments, the doped regions include a plurality of first left doped regions and a plurality of first right doped regions. A plurality of first left doped regions wrap around the bottom corner of the left side of the first gate structure. The bottom corners of the right side of the first grid structure are covered by the first right side doped regions, and the first left side doped regions and the first right side doped regions are staggered in the second direction. In some embodiments, the doped regions are spaced apart in a parallel first direction, with a spacing between any adjacent two doped regions of 1 micron to 4 microns. In some embodiments, the doped regions include a plurality of second left doped regions and a plurality of second right doped regions. A plurality of second left doped regions wrap around the bottom corner of the left side of the second gate structure. The bottom corners of the right side of the second grid structure are covered by the plurality of second right side doped regions, and the second left side doped regions and the second right side doped regions are staggered in the second direction. The second left doped region and the first right doped region are symmetrically arranged by taking a central line between the first grid structure and the second grid structure as an ax