CN-122028476-A - Trench field effect transistor semiconductor device and method of manufacturing the same

Abstract

The invention relates to a groove type field effect transistor semiconductor device and a manufacturing method thereof, and the technical scheme provided by the invention is that a series of second type grooves which discontinuously extend along the Z direction are arranged between the upper surface of a first conductive type semiconductor and the first type grooves, grooves are formed on the upper surface of the second type grooves, upper surface metal is filled into the grooves downwards, second type shielding gate electrodes are arranged in the second type grooves, a first conductive type heavy doping source region is arranged between the grooves on the upper surface of the first conductive type semiconductor, a second conductive type doping body region is arranged below the first conductive type heavy doping source region, and a second conductive type contact heavy doping region is also arranged between the second conductive type doping body region and the outer side wall of the lower part of the grooves. Compared with the existing device structure, the device structure can realize larger trench density, has lower on-resistance and better switching threshold uniformity, and has larger safe working area range and device reliability.

Inventors

• LIANG JIAJIN
• CHEN XIAOLIANG
• GAO JIANZHI
• SHAN JIANAN

Assignees

• 安建科技(深圳)有限公司

Dates

Publication Date

20260512

Application Date

20260413

Claims (18)

1. 1. A trench type field effect transistor semiconductor device comprises a first conductive type semiconductor, wherein a series of first type trenches which are distributed at intervals along the X direction and extend along the Z direction are arranged on the upper surface of the first conductive type semiconductor, a grid electrode positioned above the trenches and a first type shielding grid electrode positioned below the trenches and separated from the grid electrode are filled in the first type trenches, an upper surface metal is arranged above the first conductive type semiconductor, the trench type field effect transistor semiconductor device is characterized in that a series of second type trenches which are discontinuously extended along the Z direction are arranged between the upper surface of the first conductive type semiconductor and the first type trenches, grooves are formed on the upper surface of the second type trenches, the upper surface metal is filled into the grooves downwards, a second type shielding grid electrode is arranged in the second type trenches, the second shielding grid electrode is separated from the side walls of the trenches through a second oxide layer, a first conductive type heavily doped source region is arranged between the trenches on the upper surface of the first conductive type semiconductor, a second conductive type heavily doped source region is arranged below the first conductive type heavily doped source region, the second conductive type heavily doped source region is connected with the second conductive type heavily doped source region, the second conductive heavily doped source region is connected with the second conductive type heavily doped source region is formed on the outer side of the second conductive type semiconductor heavily doped source region, the second conductive region is connected with the second conductive heavily doped source region, and the second conductive region is in contact with the second conductive region, and the second conductive region is formed heavily doped region is in contact with the second conductive region.
2. 2. The trench fet semiconductor device of claim 1, wherein the second conductivity type contact heavily doped region has a width in the X direction of within 0.15 um.
3. 3. The semiconductor device of claim 1, wherein the second oxide layer has a lower upper surface than the second type shield gate electrode, and the recess is a semi-annular recess.
4. 4. The trench field effect transistor semiconductor device of claim 1 wherein the second type trench is a polygon having a Z-direction width C "greater than an X-direction width C'; Or the second type of grooves are regular polygons or circles.
5. 5. The trench field effect transistor semiconductor device of claim 1, wherein the first trench pitch B' is greater than or equal to the second trench pitch B ".
6. 6. The trench fet semiconductor device of claim 5, wherein the second trench pitch B "is less than the width of the second conductivity type contact heavily doped regions between the second type trenches in the Z direction, such that the second conductivity type contact heavily doped regions are connected to each other in the Z direction.
7. 7. The trench fet semiconductor device of claim 1, wherein a heavily doped current diffusion region of the first conductivity type is disposed below the doped body region of the second conductivity type, the heavily doped current diffusion region of the first conductivity type having a higher doping concentration than the drift region.
8. 8. The semiconductor device of claim 1, wherein a first type trench is further formed between the upper surface of the first conductivity type semiconductor and a portion of the second type trench to extend in the X direction.
9. 9. The trench field effect transistor semiconductor device of claim 1 wherein the second type trench has a depth less than the first type trench.
10. 10. The trench field effect transistor semiconductor device as in claim 9 wherein the lower portion of the first conductivity type semiconductor forms two or more doped regions having different doping concentrations.
11. 11. The device of claim 10, wherein the doped region includes a first drift region between the second type trenches adjacent to each other in the X direction and the first type trenches and between the second type trenches adjacent to each other in the Z direction above the doped region and a second drift region between the first type trenches adjacent to each other in the X direction and the Z direction below the second type trenches, the first drift region having a higher doping concentration than the second drift region.
12. 12. The trench field effect transistor semiconductor device of claim 9 wherein the first type of shield gate electrode in the first type of trench is a top-large bottom-small structure.
13. 13. The trench field effect transistor semiconductor device as in claim 9 wherein the second type trench has a narrower width than the first type trench, or And a second conductive shielding doped region is also arranged below the first type groove.
14. 14. The semiconductor device of claim 1, wherein the second oxide layer has a higher upper surface than the second shield gate electrode, and the recess is a hole recess.
15. 15. The trench field effect transistor semiconductor device of claim 1 wherein the heavily doped source region of the first conductivity type at the location of the first trench pitch B' is deeper than the heavily doped source region of the first conductivity type at the location of the second trench pitch B ".
16. 16. The trench field effect transistor semiconductor device of claim 1 wherein no heavily doped source region of the first conductivity type is provided between adjacent trenches of the second type.
17. 17. The manufacturing method of the trench type field effect transistor semiconductor device is characterized by comprising the following steps: Forming a first type groove and a second type groove on the upper surface of a first conductive semiconductor, forming a second oxide layer, a first type shielding gate electrode and a second type shielding gate electrode in the grooves, and forming a gate oxide layer and a gate electrode in the first type groove, wherein the height of the upper surface of the gate electrode is 0.3-1um away from the height of the upper surface of the semiconductor; Performing first-conductivity-type ion implantation, forming a deep first-conductivity-type heavily-doped source region on the side wall of the first-type groove, and forming a shallow first-conductivity-type heavily-doped source region on the upper surface of the semiconductor near the second-type groove; Thirdly, filling an insulating material in the groove to form an insulating filling layer; fourthly, photoetching is carried out, and the insulating filling layer and the second oxide layer at the top of the second type groove are etched to expose the first conductive type heavily doped source region, the second conductive type doped body region and the second type shielding gate electrode; Fifthly, performing ion implantation to form a second conductive type contact heavily doped region on the side wall of the second type groove; And sixth, filling the upper surface metal and forming the device.
18. 18. The method of manufacturing a trench fet semiconductor device according to claim 17, wherein in the fifth step, a semiconductor etching step is first performed to remove the exposed shallow heavily doped source region of the first conductivity type prior to ion implantation.

Description

Trench field effect transistor semiconductor device and method of manufacturing the same Technical Field The invention relates to a structure of a power semiconductor device, in particular to a shielded gate trench type field effect transistor device and a manufacturing method thereof. Background The shielded gate trench type field effect transistor has the characteristics of low on-resistance and high switching speed. One prior art shielded gate trench fet structure is shown in fig. 1. The left side of fig. 1 is a schematic diagram of a conventional N-type shielded gate trench fet. In order to further reduce the on-resistance of the shielded gate trench field effect transistor, the doping concentration of the drift region needs to be increased, and the resistance of the drift region needs to be reduced. Accordingly, the inter-cell trench distance (B) needs to be reduced in device structure to maintain breakdown voltage. However, as shown in the top view of the structure of the device to the right in fig. 1. The inter-cell trench distance (B) is limited by the source contact trench width (C) and the inter-cell trench-to-source contact trench distance (a) (simply referred to as trench pitch (a)). Generally, the cell trench and the source contact hole trench are formed by photolithography twice before and after, respectively. Due to the limitation of the precision of the photoetching process and the alignment deviation of the two times of photoetching, the distance (A) between the grooves is easy to be too close, so that the P+ contact doped region formed below the source contact groove influences the doping concentration of the channel region of the corresponding cell groove, and further influences the on-resistance and the switching threshold value of the device. Thus, in the above structure, the trench pitch (a) restricts further reduction of the cell size. Fig. 2 is a schematic structural diagram of a conventional improved N-type shielded gate trench fet. Compared with the structure of fig. 1, the source contact hole trench is formed in a self-aligned manner by using the pre-formed hard mask insulating layer 111. There is no space between the formed source contact hole trench and the cell trench. The structure can solve the limitation of lithography precision on the cell size. However, the structure still has the following problems that the contact resistance between the N+ doped source region and metal in the source electrode contact hole groove is larger due to the morphology of the N+ doped source region, in addition, the device structure can adjust the distance from the P+ doped region to the adjacent cell groove in a mode of increasing the etching angle and the etching depth of the source electrode contact hole groove so as to avoid influencing the doping concentration of the channel region, but the corresponding width (C) of the source electrode contact hole groove is narrowed along with the reduction of the cell size, the method is difficult to implement, and the P+ doped region is difficult to avoid influencing the doping concentration of the channel region, so that the on-resistance (particularly the on-resistance at the time of low switching threshold value) of the device is increased and the uniformity of the switching threshold value is poor. In addition, the decrease of the inter-trench distance (B) may result in a smaller on-area of the drift region, which is disadvantageous in further reducing the drift region resistance. In addition, the reduction of the cell size of the shielded gate trench field effect transistor device results in a higher channel density and a reduced safe operating area for device operation in linear applications. Thus a proper reduction of the channel density is advantageous for increasing the safe operating area of the device. Finally, the trench density of the shielded gate trench field effect transistor device increases, wafer warpage is easily caused by high surface stress, manufacturing process and device reliability are not facilitated, and the thickness reduction and yield of the thinning process are limited. Disclosure of Invention In order to solve the problems, the invention provides a trench type field effect transistor semiconductor device, which comprises a first conductive type semiconductor, wherein a series of first type trenches which are distributed at intervals along the X direction and extend along the Z direction are arranged on the upper surface of the first conductive type semiconductor, a first type shielding gate electrode which is positioned above the trenches and is positioned below the trenches and is separated from the gate electrode is filled in the first type trenches, an upper surface metal is arranged above the first conductive type semiconductor, a series of second type trenches which are discontinuously extended along the Z direction are arranged between the upper surface of the first conductive type semiconductor and the first type