CN-122028477-A - Silicon carbide multi-channel longitudinal groove type MOSFET and manufacturing method thereof

CN122028477ACN 122028477 ACN122028477 ACN 122028477ACN-122028477-A

Abstract

The invention relates to a silicon carbide multi-channel longitudinal groove type MOSFET and a manufacturing method thereof, belonging to the technical field of silicon carbide semiconductors. The device comprises a substrate, a drift region arranged on the substrate and a plurality of grooves arranged in the drift region, wherein the grooves are arranged periodically in the transverse direction, the grooves extend in the direction perpendicular to the surface of the substrate, a gate oxide layer and a gate electrode positioned on the gate oxide layer are respectively arranged on two sides in the grooves, a channel region is formed between adjacent grooves and at the bottom of the grooves in the drift region, a source electrode region and a body contact region are formed in the channel region, an intermetallic dielectric layer is formed between the surface of the gate electrode and the source electrode region, a top-layer source electrode metal is formed on the source electrode region, and an ohmic contact layer is formed between the source electrode region and the top-layer source electrode metal. According to the device disclosed by the invention, the reverse conducting channels are formed on the side wall and the bottom of the groove at the same time, so that conducting current flows in parallel in the longitudinal direction and the transverse direction, and the number of the effective conducting channels is obviously increased.

Inventors

Handoc Linawich
DU ZELIN
ZHONG YU
XU XIANGANG
HAN JISHENG

Assignees

山东大学

Dates

Publication Date: 20260512
Application Date: 20260416

Claims (10)

1. A silicon carbide multi-channel longitudinal groove type MOSFET is characterized by comprising a substrate, a drift region arranged on the substrate and a plurality of grooves arranged in the drift region, wherein the grooves are arranged periodically in the transverse direction, the grooves extend in the direction perpendicular to the surface of the substrate, a gate oxide layer and a grid electrode positioned on the gate oxide layer are respectively arranged on two sides in the grooves, a channel region is arranged between adjacent grooves and at the bottom of the groove in the drift region, a source region and a body contact region are arranged in the channel region, an intermetallic dielectric layer is arranged on the side face of the grid electrode, the intermetallic dielectric layer extends to a source region, a top layer source metal is arranged on the source region, an ohmic contact layer is arranged between the source region and the top layer source metal, a bottom layer drain metal is arranged below the substrate, and ohmic contact is formed between the bottom layer drain metal and the substrate.
2. The silicon carbide multi-channel vertical trench MOSFET of claim 1, wherein the drift region is an N-type lightly doped silicon carbide epitaxial layer, the doping element is nitrogen, and the doping concentration is 5 x 10 14 cm -3 -5×10 16 cm -3 .
3. The silicon carbide multi-channel vertical trench MOSFET according to claim 1, wherein the trench depth is 1.0-1.5 μm and the trench width is 4.0-6.0 μm.
4. The silicon carbide multi-channel vertical trench MOSFET of claim 1, wherein the gate oxide layer is a silicon dioxide layer having a thickness of 40-70 nm a.
5. The silicon carbide multi-channel vertical trench MOSFET of claim 1, wherein the gate material is doped polysilicon or a metal gate material.
6. The silicon carbide multi-channel vertical trench MOSFET according to claim 1, wherein the doping element of the channel region is aluminum, the doping concentration is 5 x 10 16 -5×10 17 cm -3 , and the doping depth is 0.8 μm to 1.3 μm.
7. The silicon carbide multi-channel vertical trench MOSFET of claim 1, comprising one or more of the following conditions: a. The substrate is a heavily doped N-type 4H-SiC substrate, the doping element is nitrogen, and the doping concentration is more than 1 multiplied by 10 19 cm -3 , the substrate is a Si polar (0001) crystal face substrate, and the substrate has a bias cut angle of 4 degrees along the [11-20] direction; b. The source electrode region is a heavily doped N-type region, the doping element is nitrogen, the doping concentration is more than 1 multiplied by 10 18 cm -3 , and the doping depth is 0.3-1.0 mu m; c. The doping element of the body contact region is aluminum, the doping concentration is more than 1 multiplied by 10 18 cm -3 , and the doping depth is 0.5-1.3 mu m; d. The material of the intermetallic dielectric layer is silicon dioxide or a low-dielectric-constant dielectric material, and the low-dielectric-constant dielectric material is one or more selected from fluorine-doped silicon dioxide, carbon-doped silicon oxide and porous low-dielectric-constant materials; e. The top-layer source electrode metal is of a laminated structure, the laminated structure comprises a barrier layer and a conductive layer, the barrier layer is one or more of a titanium layer and a titanium nitride layer, and the conductive layer is an aluminum layer or an aluminum copper alloy layer.
8. A method of manufacturing a silicon carbide multi-channel vertical trench MOSFET for use in the silicon carbide multi-channel vertical trench MOSFET of claim 1, comprising the steps of: (1) Providing a substrate, and forming a drift region on the substrate; (2) Forming a plurality of trenches in the drift region; (3) Forming a channel region between adjacent trenches of the drift region and at the bottom of the trench; (4) Forming a source region and a body contact region in the channel region; (5) Forming a gate oxide layer on the side wall of the groove and a gate electrode positioned on the gate oxide layer; (6) Forming an intermetallic dielectric layer between the surface of the grid electrode and the source electrode region, and manufacturing an ohmic contact layer; (7) Forming a top source metal on the source region; (8) An underlying drain metal is formed under the substrate.
9. The method of fabricating a silicon carbide multi-channel vertical trench MOSFET according to claim 8, comprising one or more of the following conditions: i. In the step (1), a drift region is formed on the substrate through an epitaxial growth process; Forming a plurality of etching windows which are periodically arranged along the transverse direction in the first oxidation layer through a photoetching process, and anisotropically etching the drift region by taking the etching windows as a trench etching mask to form a plurality of trenches which extend along the direction vertical to the surface of the substrate, wherein the first oxidation layer is a silicon dioxide layer; in the step (3), a dielectric material is deposited on the side wall of the groove to form a spacing layer, aluminum ion implantation is carried out on the surface of the drift region, and a channel region is formed between adjacent grooves and at the bottom of the grooves, wherein the dielectric material is silicon dioxide or silicon nitride; The method for forming the source region and the body contact region in the step (4) comprises the steps of depositing dielectric materials on the side walls of the grooves again to thicken the spacer layers, carrying out nitrogen ion implantation on the surface of the channel region by taking the spacer layers as self-aligned masks to form the source region, limiting an implantation region by adopting photoetching masks, carrying out aluminum ion implantation on the midpoint of the surface of the channel region to form the body contact region, finally cleaning and removing the spacer layers, carrying out post-implantation annealing on the surface of a wafer, and taking silicon dioxide or silicon nitride as the dielectric materials.
10. The method of fabricating a silicon carbide multi-channel vertical trench MOSFET according to claim 8, comprising one or more of the following conditions: In the step (5), the gate oxide layer and the gate electrode on the gate oxide layer are formed by a thermal oxidation process on the wafer surface in the step (4), and then a gate film is formed on the silicon dioxide layer by a deposition process, and the gate oxide layer and the gate film are etched to form a gate electrode; in the step (6), the forming process of the intermetallic dielectric layer and the ohmic contact layer comprises the steps of forming the intermetallic dielectric layer between the surface of the grid electrode and the source electrode region through a plasma enhanced chemical vapor deposition process, forming a contact hole through photoetching and etching processes, and forming ohmic contact layers in the source electrode region and the body contact region through windowing; In the step (6), forming a top source metal layer on the source region through a physical vapor deposition process; In the step (7), the formation process of the bottom drain metal is that the wafer after the step (6) is subjected to passivation treatment, and the bottom drain metal is formed under the substrate through metal deposition and annealing processes.

Description

Silicon carbide multi-channel longitudinal groove type MOSFET and manufacturing method thereof Technical Field The invention belongs to the technical field of silicon carbide semiconductors, and particularly relates to a silicon carbide multi-channel longitudinal groove type MOSFET and a manufacturing method thereof. Background The MOSFET (metal-oxide-semiconductor field effect transistor) has become a core switching device in a modern power electronic system by virtue of the remarkable advantages of low conduction loss, high switching speed, high input impedance, small driving loss and the like, and is widely applied to various power management and power conversion scenes such as switching power supplies, inverters, charging piles, electric control of new energy automobiles and the like. With the trend of high frequency, miniaturization and high efficiency, the power device has a core development trend, and the research emphasis has been on further reducing the conduction loss of the device and improving the current processing capability per unit area. The trench MOSFET forms a vertical trench structure in the semiconductor material through an etching process, so that the conductive channels are longitudinally distributed along the side wall of the trench, and the effective channel width can be greatly increased under the condition that the area of a chip is unchanged, thereby effectively reducing the specific on-resistance, and becoming a main flow structural scheme of the high-voltage power MOSFET. However, the conventional trench MOSFET has obvious performance bottlenecks, namely, the devices usually form longitudinal conduction channels only on the side walls of the two sides of the trench, the bottom area of the trench hardly participates in conduction, the surface area of the semiconductor is not fully utilized, and the channel density and the conduction performance still have a larger improvement space. In addition, the bottom of the groove is easy to form an electric field concentration area, the voltage resistance and the reliability of the device are affected, and the severe requirements of application scenes of higher voltage and higher power density are difficult to meet. Disclosure of Invention Aiming at the defects of the prior art, the invention aims to provide a silicon carbide multi-channel longitudinal groove type MOSFET and a manufacturing method thereof. The invention mainly solves the technical problems of how to further improve the channel utilization efficiency in the groove type MOSFET and improve the electric field distribution at the bottom of the groove so as to reduce the on-resistance while ensuring the voltage endurance capability. The technical scheme of the invention is as follows: The invention provides a silicon carbide multi-channel longitudinal groove type MOSFET which comprises a substrate, a drift region arranged on the substrate and a plurality of grooves arranged in the drift region, wherein the grooves are arranged periodically in the transverse direction, the grooves extend in the direction perpendicular to the surface of the substrate, a gate oxide layer and a grid electrode positioned on the gate oxide layer are respectively arranged on two sides in the grooves, a channel region is arranged between adjacent grooves and at the bottom of the groove in the drift region, a source region and a body contact region are arranged in the channel region, an intermetallic dielectric layer is arranged on the side face of the grid electrode, the intermetallic dielectric layer extends to a source region, a top layer source metal is arranged on the source region, an ohmic contact layer is arranged between the source region and the top layer source metal, a bottom layer drain metal is arranged below the substrate, and ohmic contact is formed between the bottom layer drain metal and the substrate. When grid voltage is applied to the grid electrode, the channel region forms a longitudinal inversion channel on the side wall of the groove to conduct current carriers along the depth direction of the groove, and meanwhile, a transverse inversion channel is formed in the channel region at the bottom of the groove to conduct current carriers along the transverse direction between adjacent grooves. According to the invention, the substrate is preferably a heavily doped N-type 4H-SiC substrate, the doping element is nitrogen, the doping concentration is more than 1 multiplied by 10 19cm-3, and the substrate is a (0001) crystal face substrate with Si polarity and has a bias cut angle of 4 degrees along the [11-20] direction. The substrate is used for forming a drain region of a semiconductor device and providing a low-resistance current output channel. According to the invention, the drift region is an N-type lightly doped silicon carbide epitaxial layer, the doping element is nitrogen, and the doping concentration is 5×10 14cm-3-5×1016cm-3. The doping depth of the drift region is set accor