CN-122028478-A - Preparation method of semiconductor structure, memory and electronic equipment

Abstract

The disclosure relates to a method for manufacturing a semiconductor structure, the semiconductor structure, a memory and an electronic device. A preparation method of a semiconductor structure comprises the steps of providing a substrate, forming a channel layer on the substrate, forming a sacrificial layer with a preset thickness on the channel layer, wherein crystal lattice vacancies are formed in a part, close to the sacrificial layer, of the channel layer, repairing the crystal lattice vacancies based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer, and forming a gate dielectric layer on the interface layer. In the preparation method of the semiconductor structure, crystal lattice vacancies are arranged in the part of the channel layer, which is close to the sacrificial layer, and in the process of forming the interface layer on the channel layer, the crystal lattice vacancies can be repaired based on the sacrificial layer and the channel layer so as to improve the interface quality of the interface layer. Therefore, the influence of the interface state between the gate dielectric layer and the channel layer on the device can be improved, and the electrical performance and reliability of the device are improved.

Inventors

• MA XUELI
• XIANG JINJUAN
• WANG GUILEI
• ZHAO CHAO

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241108

Claims (11)

1. 1. A method of fabricating a semiconductor structure, the method comprising: Providing a substrate and forming a channel layer on the substrate; Forming a sacrificial layer with a preset thickness on the channel layer, wherein crystal lattice vacancies are arranged in a part of the channel layer close to the sacrificial layer; repairing the crystal lattice vacancies based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer; and forming a gate dielectric layer on the interface layer.
2. 2. The method of claim 1, wherein the crystal lattice vacancies comprise oxygen vacancies, and wherein the repairing the crystal lattice vacancies based on the sacrificial layer and the channel layer to obtain an interfacial layer on the channel layer comprises: and performing an in-situ annealing process on the structure after the sacrificial layer is formed, so that the contact interface of the sacrificial layer and the channel layer reacts to form the interface layer.
3. 3. The method of claim 2, wherein the in-situ annealing process comprises at least one of the following features: the annealing temperature of the in-situ annealing process is 300-700 ℃; The annealing time range of the in-situ annealing process is 1min-60min; The annealing atmosphere of the in-situ annealing process is a gas atmosphere formed by oxygen, ozone or an inert mixed gas containing oxygen.
4. 4. The method of fabricating a semiconductor structure according to any one of claims 1-3, wherein the predetermined thickness is in a range of
5. 5. A method of fabricating a semiconductor structure according to any one of claims 1 to 3, wherein the sacrificial layer material comprises an oxide.
6. 6. The method of any of claims 1-3, wherein the channel layer, the sacrificial layer, the interfacial layer, and the gate dielectric layer are formed in the same vacuum environment.
7. 7. The method of claim 1, wherein the sacrificial layer and the gate dielectric layer are made of the same or different materials.
8. 8. The method of claim 1, further comprising, after forming a gate dielectric layer on the interfacial layer: And carrying out an annealing process on the obtained structure after the gate dielectric layer is formed, wherein the annealing process comprises at least one of the following characteristics: the annealing temperature of the annealing process is 300-700 ℃; The annealing time range of the annealing process is 1min-60min; The annealing atmosphere of the annealing process is a gas atmosphere formed by oxygen, ozone, nitrogen or an inert mixed gas containing oxygen.
9. 9. The semiconductor structure is characterized by comprising a substrate, and a channel layer, an interface layer and a gate dielectric layer which are positioned on the substrate from bottom to top, wherein the interface layer is a crystal lattice vacancy repairing layer.
10. 10. A memory comprising the semiconductor structure of claim 9 or comprising the semiconductor structure formed by the method of fabricating the semiconductor structure of any one of claims 1 to 8.
11. 11. An electronic device comprising the memory of claim 10.

Description

Preparation method of semiconductor structure, memory and electronic equipment Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure, a memory, and an electronic device. Background Due to good post-process compatibility and ultra-long data retention time, thin film transistors are increasingly important in emerging applications and are increasingly widely used. For example, the method has a great deal of application in the fields of flexible display, internet of things, wearable electronics, memory and the like. However, any minor differences and imperfections in process production may have an impact on the performance of the device, resulting in degradation and instability of the electrical performance of the device. Thus, there is a need for a method to ameliorate the effects of the above problems on devices. Disclosure of Invention Based on the above, the present disclosure provides a method for manufacturing a semiconductor structure, a memory and an electronic device, which can improve the influence of an interface state between a gate dielectric layer and a channel layer on a device. According to some embodiments, an aspect of the present disclosure provides a method for preparing a semiconductor structure, the method comprising: Providing a substrate and forming a channel layer on the substrate; forming a sacrificial layer with a preset thickness on the channel layer, wherein crystal lattice vacancies are arranged in the part of the channel layer close to the sacrificial layer Repairing crystal lattice vacancies based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer; And forming a gate dielectric layer on the interface layer. In some embodiments, crystal lattice vacancies comprise oxygen vacancies, and repairing the crystal lattice vacancies based on the sacrificial layer and the channel layer to obtain an interface layer on the channel layer comprises performing an in situ annealing process on the resulting structure after forming the sacrificial layer such that the contact interface of the sacrificial layer and the channel layer reacts to form the interface layer. In some embodiments, the annealing temperature of the in-situ annealing process is in the range of 300 ℃ to 700 ℃; In some embodiments, the annealing time of the in-situ annealing process ranges from 1min to 60min; In some embodiments, the annealing atmosphere of the in-situ annealing process is a gas atmosphere formed from oxygen, ozone, or an inert mixed gas containing oxygen. In some embodiments, the predetermined thickness ranges from In some embodiments, the material of the sacrificial layer comprises an oxide. In some embodiments, the channel layer, the sacrificial layer, the interface layer, and the gate dielectric layer are formed in the same vacuum environment. In some embodiments, the sacrificial layer and the gate dielectric layer are made of the same or different materials. In some embodiments, after forming the gate dielectric layer on the interfacial layer, the method further includes performing an annealing process on the resulting structure after forming the gate dielectric layer. In some embodiments, the annealing temperature of the annealing process is in the range of 300 ℃ to 700 ℃; In some embodiments, the annealing time of the annealing process ranges from 1min to 60min; in some embodiments, the annealing atmosphere of the annealing process is a gas atmosphere formed from oxygen, ozone, nitrogen, or an inert mixed gas containing oxygen. According to some embodiments, a further aspect of the present disclosure provides a semiconductor structure comprising a substrate, and a channel layer, an interface layer, and a gate dielectric layer located on the substrate from bottom to top, wherein the interface layer is a crystal lattice vacancy repair layer. According to some embodiments, a further aspect of the present disclosure provides a memory comprising the semiconductor structure described above, or comprising a semiconductor structure formed by the method of manufacturing a semiconductor structure described above. According to some embodiments, a further aspect of the present disclosure provides an electronic device comprising the memory described above. Embodiments of the present disclosure may/have at least the following advantages: In the method for manufacturing the semiconductor structure provided by the embodiment of the disclosure, crystal lattice vacancies are arranged in the part, close to the sacrificial layer, of the channel layer, and in the process of forming the interface layer on the channel layer, the crystal lattice vacancies can be repaired based on the sacrificial layer and the channel layer, so that the interface quality of the interface layer is improved. Therefore, the influence of the interface state between the gate dielectric layer and the