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CN-122028479-A - Semiconductor device with engineering gate dielectric stack and preparation method thereof

CN122028479ACN 122028479 ACN122028479 ACN 122028479ACN-122028479-A

Abstract

The invention relates to a semiconductor device with an engineering gate dielectric stack and a preparation method thereof, wherein the top surface of a semiconductor substrate is provided with a gate stack layer which transversely extends from one source electrode to the other source electrode and covers a drift region and a channel, the gate stack layer comprises a high dielectric constant layer, a tunneling layer, a floating dielectric layer which covers the high dielectric constant layer and the tunneling layer, a second dielectric layer which covers the floating dielectric layer, a control gate layer which covers the second dielectric layer, an interlayer dielectric layer which is wrapped outside the gate stack layer, an active metal layer which is wrapped outside the interlayer dielectric layer, and a back metal layer which is arranged on the bottom surface of the semiconductor substrate.

Inventors

  • Tommaso Steconi
  • Nick Schneider
  • Paula Diaz Regoza
  • Lars Noel Christian

Assignees

  • 赛晶亚太半导体科技(浙江)有限公司
  • 瑞士半导体科技有限公司

Dates

Publication Date
20260512
Application Date
20260415

Claims (20)

  1. 1. A semiconductor device having an engineered gate dielectric stack, comprising: A semiconductor substrate (1), wherein a drain electrode (101) of a first conductivity type is arranged on the semiconductor substrate (1), a drift region (102) of the first conductivity type is arranged above the drain electrode (101), channels (103) of a second conductivity type are arranged on the top surface of the drift region (102) at intervals, and a source electrode (104) of the first conductivity type is arranged in each channel (103); the top surface of the semiconductor substrate (1) is provided with a grid stacking layer which transversely extends from one source electrode (104) to the other source electrode (104) adjacent to the other source electrode and covers the drift region (102) and the channel (103); The gate stack layer comprises a high dielectric constant layer (2) which transversely extends from one adjacent source electrode (104) to the other source electrode (104) and covers the channel (103) and the drift region (102), one side or two sides of the high dielectric constant layer (2) are provided with tunneling layers (6) which are prepared by adopting wide band gap and low dielectric constant materials, each tunneling layer (6) is gapless with the adjacent high dielectric constant layer (2), each tunneling layer (6) transversely deviates from the channel (103) and is not overlapped with the channel (103), the gate stack layer further comprises a floating dielectric layer (3) which covers the high dielectric constant layer (2) and the tunneling layers (6), a second dielectric layer (4) which covers the floating dielectric layer (3) and a control gate layer (5) which covers the second dielectric layer (4); an interlayer dielectric (7) is wrapped outside the grid stacking layer; An active metal layer (11) is wrapped outside the interlayer dielectric (7); a back metal layer (12) is provided on the bottom surface of the semiconductor substrate (1).
  2. 2. The semiconductor device with engineered gate dielectric stack of claim 1, wherein: the thickness of the tunneling layer (6) is smaller than the thickness of the high dielectric constant layer (2); In the lateral direction, the first width (d) of the interval between the tunneling layer (6) and the channel (103) is 10-500nm.
  3. 3. The semiconductor device with engineered gate dielectric stack of claim 1, wherein: The relative dielectric constant of the tunneling layer (6) is less than or equal to 5, and the wide band gap is more than or equal to 6eV; The thickness of the tunneling layer (6) is 1-10mm; The thickness of the high dielectric constant layer (2) is 20-100nm; the thickness of the floating dielectric layer (3) is 10-150nm; The material of the high dielectric constant layer (2) is at least one of hafnium oxide, zirconium oxide, aluminum oxide, silicon nitride, lanthanum aluminate or hafnium aluminum oxide; The tunneling layer (6) is made of at least one of silicon dioxide, aluminum oxide or silicon oxynitride; The second dielectric layer (4) is made of at least one of oxide, nitride, high-dielectric-constant dielectric or oxide, nitride and oxide stack; the floating dielectric layer (3) is made of polysilicon or metal; The control grid layer (5) is made of polysilicon or metal; The high dielectric constant layer (2) is prepared from a high dielectric constant material.
  4. 4. A method of manufacturing a semiconductor device with an engineered gate dielectric stack as in any of claims 1-3, comprising the steps of: Preparing a grid stacking layer on the top surface of a semiconductor substrate (1), preparing a high dielectric constant layer (2) on the top surface of the semiconductor substrate (1), masking and etching the high dielectric constant layer (2), removing part of the high dielectric constant layer (2) above a source electrode (104), and depositing or growing a wide band gap and low dielectric constant material on the position where the high dielectric constant layer (2) is removed to form a tunneling layer (6); Preparing a floating dielectric layer (3) on the tunneling layer (6) and the high dielectric constant layer (2), preparing a second dielectric layer (4) on the floating dielectric layer (3), and preparing a control gate layer (5) on the second dielectric layer (4); Preparing an interlayer dielectric (7) outside the gate stack; Preparing a source metal layer (11) outside the interlayer dielectric (7); A back metal layer (12) is prepared on the bottom surface of a semiconductor substrate (1).
  5. 5. The method of manufacturing a semiconductor device with an engineered gate dielectric stack of claim 4, wherein: The thickness of the tunneling layer (6) is smaller than that of the high dielectric constant layer (2); preparing a high dielectric constant layer (2) by adopting atomic layer deposition or chemical vapor deposition; the preparation process of the tunneling layer (6) comprises the following steps: Depositing a wide band gap, low dielectric constant material by atomic layer deposition at 50-400deg.C on the position where the high dielectric constant layer (2) is removed to form a tunneling layer (6), and annealing at 200-600deg.C under a forming gas after deposition, or And rapidly thermally oxidizing and growing a wide band gap and low dielectric constant material on the position of the removed high dielectric constant layer (2) to form a tunneling layer (6).
  6. 6. A semiconductor device having an engineered gate dielectric stack, characterized by: A semiconductor substrate (1), wherein a drain electrode (101) of a first conductivity type is arranged on the semiconductor substrate (1), a drift region (102) of the first conductivity type is arranged above the drain electrode (101), channels (103) of a second conductivity type are arranged on the top surface of the drift region (102) at intervals, and a source electrode (104) of the first conductivity type is arranged in each channel (103); the top surface of the semiconductor substrate (1) is provided with a grid stacking layer which transversely extends from one source electrode (104) to the other source electrode (104) adjacent to the other source electrode and covers the drift region (102) and the channel (103); The gate stack layer comprises an insulating layer (8) which is positioned above a drift region (102) and is prepared by oxide, high dielectric constant layers (2) are respectively arranged on two sides of the insulating layer (8), one end of each high dielectric constant layer (2) extends to the drift region (102), the other end of each high dielectric constant layer extends to a source electrode (104) and covers a channel (103), no gap exists between each high dielectric constant layer (2) and the insulating layer (8), a tunneling layer (6) which is prepared by a wide-band-gap low dielectric constant dielectric material is arranged on one side of each high dielectric constant layer (2), no gap exists between each tunneling layer (6) and the adjacent high dielectric constant layer (2), and each tunneling layer (6) transversely deviates from the channel (103) and does not overlap with the channel (103); the semiconductor device further comprises a floating dielectric layer (3) covering the high dielectric constant layer (2) and the tunneling layer (6), a second dielectric layer (4) covering the floating dielectric layer (3), a control gate layer (5) covering the second dielectric layer (4), and an interlayer dielectric (7) wrapping the gate stack layer; An active metal layer (11) is wrapped outside the interlayer dielectric (7); a back metal layer (12) is provided on the bottom surface of the semiconductor substrate (1).
  7. 7. The semiconductor device with engineered gate dielectric stack of claim 6, wherein: the thickness of the insulating layer (8) is larger than that of the high dielectric constant layer (2); the thickness of the tunneling layer (6) is smaller than the thickness of the high dielectric constant layer (2); In the lateral direction, the width of the source electrode between the tunneling layer (6) and the channel (103) is 10-500nm.
  8. 8. The semiconductor device with engineered gate dielectric stack of claim 6, wherein: the relative dielectric constant of the dielectric material of the tunneling layer (6) is less than or equal to 5, and the wide band gap is more than or equal to 6eV; The thickness of the tunneling layer (6) is 1-10mm; The thickness of the high dielectric constant layer (2) is 20-100nm; the thickness of the floating dielectric layer (3) is 10-150nm; The tunneling layer (6) is made of at least one of silicon dioxide, aluminum oxide or silicon oxynitride; The material of the high dielectric constant layer (2) is at least one of hafnium oxide, zirconium oxide, aluminum oxide, silicon nitride, lanthanum aluminate or hafnium aluminum oxide; The second dielectric layer (4) is made of at least one of oxide, nitride, high-dielectric-constant dielectric or oxide, nitride and oxide stack; the floating dielectric layer (3) is made of polysilicon or metal; The control grid layer (5) is made of polysilicon or metal; The insulating layer (8) is made of at least one of alumina, silicon oxide, silicon nitride or oxide-nitride-oxide stack; The high dielectric constant layer (2) is prepared from a high dielectric constant material.
  9. 9. A method of manufacturing a semiconductor device with an engineered gate dielectric stack as in any of claims 6-8, comprising the steps of: Preparing a grid stacking layer on the top surface of a semiconductor substrate (1), preparing a high dielectric constant dielectric on the top surface of the semiconductor substrate (1) to form a high dielectric constant layer (2), etching the high dielectric constant layer (2), removing part of the high dielectric constant layer (2) above a source electrode (104) and part of the high dielectric constant layer (2) above a drift region, depositing or growing a wide band gap and low dielectric constant material above the source electrode (104) to form a tunneling layer (6), depositing an oxide above the drift region (102) to form an insulating layer (8), preparing a floating dielectric layer (3) on the tunneling layer (6), the high dielectric constant layer (2) and the insulating layer (8), preparing a second dielectric layer (4) on the floating dielectric layer (3), and preparing a control grid layer (5) on the second dielectric layer (4); Preparing an interlayer dielectric (7) outside the gate stack; Preparing a source metal layer (11) outside the interlayer dielectric (7); A back metal layer (12) is prepared on the bottom surface of a semiconductor substrate (1).
  10. 10. The method of manufacturing a semiconductor device with an engineered gate dielectric stack of claim 9, wherein: The preparation steps of the tunneling layer (6) and the insulating layer (8) comprise: Patterning the high-k layer (2), removing a portion of the high-k layer (2) above the source (104) and above the drift region (102), while the high-k layer (2) above the channel remains; performing a first rapid thermal oxidation to grow oxide within the source (104) and drift region (102) windows, substantially without oxide growth on the high dielectric constant layer (2); a second rapid thermal oxidation is performed, masking the growth of the source (104) followed by regrowth of oxide such that additional oxide grows over the drift region (102) window, resulting in an insulating layer (8) having a thickness greater than the high dielectric constant layer (2).
  11. 11. A semiconductor device with an engineered gate dielectric stack is characterized by comprising A semiconductor substrate (1), wherein a drain electrode (101) of a first conductivity type is arranged on the semiconductor substrate (1), a drift region (102) of the first conductivity type is arranged above the drain electrode (101), channels (103) of a second conductivity type are arranged on the top surface of the drift region (102) at intervals, and a source electrode (104) of the first conductivity type is arranged in each channel (103); the top surface of the semiconductor substrate (1) is provided with a grid stacking layer which transversely extends from one source electrode (104) to the other source electrode (104) adjacent to the other source electrode and covers the drift region (102) and the channel (103); The grid stacking layer comprises a high dielectric constant layer (2) which transversely extends from one adjacent source electrode (104) to the other source electrode (104) and covers the channel (103) and the drift region (102), a tunneling layer (6) which is prepared by adopting a wide band gap and low dielectric constant material is arranged on one side or two sides of the high dielectric constant layer (2), the tunneling layer (6) is gapless with the adjacent high dielectric constant layer (2), the tunneling layer (6) is transversely deviated from the channel (103) and is not overlapped with the channel (103), a floating dielectric layer (3) covers the high dielectric constant layer (2) and the tunneling layer (6), a second dielectric layer (4) covers the floating dielectric layer (3), and a control grid layer (5) arranged on the second dielectric layer (4); The control grid layer (5) comprises a central control grid plate (51), wherein the central control grid plate (51) covers a channel (103) and a drift region (102), a margin is transitionally extended above a corresponding source electrode (104), programming grid plates (52) on two sides of the central control grid plate (51) are respectively arranged, and an isolation gap is arranged between each programming grid plate (52) and the central control grid plate (51), each programming grid plate (52) is positioned above a corresponding tunneling layer (6), and each programming grid plate (52) is not overlapped with the channel (103) in the transverse direction; Preparing an interlayer dielectric (7) outside the gate stack layer, the interlayer dielectric (7) filling the isolation gap; An active metal layer (11) is wrapped outside the interlayer dielectric (7); a back metal layer (12) is provided on the bottom surface of the semiconductor substrate (1).
  12. 12. The semiconductor device with engineered gate dielectric stack of claim 11, wherein: an insulation gap is arranged between the programming grid plate (52) and the central control grid plate (51); the thickness of the tunneling layer (6) is smaller than the thickness of the high dielectric constant layer (2); In the lateral direction, the width of the source between the tunneling layer (6) and the channel (103) is 10-500nm.
  13. 13. The semiconductor device with engineered gate dielectric stack of claim 11, wherein: The width of each programming grid plate (52) is larger than the width of the tunneling layer (6), and the difference value between the width of the programming grid plate (52) and the width of the tunneling layer (6) is more than or equal to e/2, wherein e is the width of an insulation gap between the programming grid plate (52) and the central control grid plate (51); Each programming gate plate (52) further extends laterally beyond the perimeter of the tunneling portion by 10-200nm over the high dielectric constant portion while maintaining a lateral separation from the channel region by a distance sufficient to avoid overlapping with the channel.
  14. 14. The semiconductor device with engineered gate dielectric stack of claim 11, wherein: the width of the tunneling layer (6) is larger than that of the programming gate plate (52), and the difference value between the width of the tunneling layer (6) and the width of the programming gate plate (52) is more than or equal to e/2, wherein e is the width of an insulation gap between the programming gate plate (52) and the central control gate plate (51).
  15. 15. The semiconductor device with engineered gate dielectric stack of claim 11, wherein: the relative dielectric constant of the dielectric material of the tunneling layer (6) is less than or equal to 5, and the wide band gap is more than or equal to 6eV; The thickness of the tunneling layer (6) is 1-10mm; The thickness of the high dielectric constant layer (2) is 20-100nm; the thickness of the floating dielectric layer (3) is 10-150nm; The tunneling layer (6) is made of at least one of silicon dioxide, aluminum oxide or silicon oxynitride; The material of the high dielectric constant layer (2) is at least one of hafnium oxide, zirconium oxide, aluminum oxide, silicon nitride, lanthanum aluminate or hafnium aluminum oxide; The second dielectric layer (4) is made of at least one of oxide, nitride, high-dielectric-constant dielectric or oxide, nitride and oxide stack; the floating dielectric layer (3) is made of polysilicon or metal; The control grid layer (5) is made of polysilicon or metal; The high dielectric constant layer (2) is prepared from a high dielectric constant material.
  16. 16. A method of manufacturing a semiconductor device with an engineered gate dielectric stack as in any of claims 11-15, comprising the steps of: Preparing a grid stacking layer on the top surface of a semiconductor substrate (1), specifically depositing a high-dielectric-constant dielectric on the top surface of the semiconductor substrate (1) to form a high-dielectric-constant layer (2), etching the high-dielectric-constant layer (2), removing part of the high-dielectric-constant layer (2) above a source electrode (104), depositing or growing a wide band gap and low-dielectric-constant material on the position where the high-dielectric-constant layer (2) is removed to form a tunneling layer (6), preparing a floating dielectric layer (3) on the tunneling layer (6) and the high-dielectric-constant layer (2), preparing a second dielectric layer (4) on the floating dielectric layer (3), preparing a control gate layer (5) on the second dielectric layer (4), etching the control gate layer (5), separating a central control gate plate (51) and a programming gate plate (52), wherein the central control gate plate (51) covers a channel (103) and a drift region (102), and a allowance is formed by transition extension on the corresponding source electrode (104), a gap is arranged between the programming gate plate (52) and the central control gate plate (103), and each programming gate plate (52) is positioned above the corresponding tunneling layer (6) and does not overlap with the channel limiting layer (6); Preparing an interlayer dielectric (7) outside the gate stack layer, the interlayer dielectric (7) filling the isolation gap; Preparing a source metal layer (11) outside the interlayer dielectric (7); A back metal layer (12) is prepared on the bottom surface of a semiconductor substrate (1).
  17. 17. The method of manufacturing according to claim 16, wherein: the thickness of the tunneling layer (6) is smaller than the thickness of the high dielectric constant layer (2); preparing a high dielectric constant layer (2) by adopting atomic layer deposition or chemical vapor deposition; the preparation method of the tunneling layer (6) comprises the following steps: The tunneling layer (6) is prepared by depositing a wide band gap, low dielectric constant material by atomic layer deposition at 50-400 ℃, and annealing at 200-600 ℃ is performed under forming gas after deposition, or the wide band gap, low dielectric constant material is grown where the high dielectric constant layer (2) is removed.
  18. 18. A semiconductor device with an engineered gate dielectric stack is characterized by comprising A semiconductor substrate (1), wherein a drain electrode (101) of a first conductivity type is arranged on the semiconductor substrate (1), a drift region (102) of the first conductivity type is arranged above the drain electrode (101), channels (103) of a second conductivity type are arranged on the top surface of the drift region (102) at intervals, and a source electrode (104) of the first conductivity type is arranged in each channel (103); the top surface of the semiconductor substrate (1) is provided with a grid stacking layer which transversely extends from one source electrode (104) to the other source electrode (104) adjacent to the other source electrode and covers the drift region (102) and the channel (103); The gate stack layer comprises an insulating layer (8) which is positioned above a drift region (102) and is prepared by oxide, high dielectric constant layers (2) are respectively arranged on two sides of the insulating layer (8), one end of each high dielectric constant layer (2) extends to the drift region (102), the other end of each high dielectric constant layer extends to a source electrode (104) and covers a channel (103), tunneling layers (6) which are prepared by wide band gap and low dielectric constant materials are arranged on one side or two sides of each high dielectric constant layer (2), no gap exists between each tunneling layer (6) and the adjacent high dielectric constant layer (2), and each tunneling layer (6) is deviated from the channel (103) in the transverse direction and is not overlapped with the channel (103); The semiconductor device further comprises a floating dielectric layer (3) covering the high dielectric constant layer (2) and the tunneling layer (6), a second dielectric layer (4) covering the floating dielectric layer (3), and a control grid layer (5) covering the second dielectric layer (4); The control grid layer (5) comprises a central control grid plate (51), wherein the central control grid plate (51) covers a channel (103) and a drift region (102), a margin is transitionally extended above a corresponding source electrode (104), programming grid plates (52) on two sides of the central control grid plate (51) are respectively arranged, and an isolation gap is arranged between each programming grid plate (52) and the central control grid plate (51); Preparing an interlayer dielectric (7) outside the gate stack layer, the interlayer dielectric (7) filling the isolation gap; An active metal layer (11) is wrapped outside the interlayer dielectric (7); a back metal layer (12) is provided on the bottom surface of the semiconductor substrate (1).
  19. 19. The semiconductor device with engineered gate dielectric stack of claim 18, wherein: the width of the tunneling layer (6) is larger than that of the programming gate plate (52), and the difference value between the width of the tunneling layer (6) and the width of the programming gate plate (52) is more than or equal to e/2, wherein e is the width of an insulation gap between the programming gate plate (52) and the central control gate plate (51).
  20. 20. The semiconductor device with engineered gate dielectric stack of claim 18, wherein: the thickness of the insulating layer (8) is larger than that of the high dielectric constant layer (2); the thickness of the tunneling layer (6) is smaller than the thickness of the high dielectric constant layer (2); The width of the source electrode between the tunneling layer (6) and the channel (103) is 10-500nm; the relative dielectric constant of the dielectric material of the tunneling layer (6) is less than or equal to 5, and the wide band gap is more than or equal to 6eV; The thickness of the tunneling layer (6) is 1-10mm; The thickness of the high dielectric constant layer (2) is 20-100nm; the thickness of the floating dielectric layer (3) is 10-150nm; The tunneling layer (6) is made of at least one of silicon dioxide, aluminum oxide or silicon oxynitride; The material of the high dielectric constant layer (2) is at least one of hafnium oxide, zirconium oxide, aluminum oxide, silicon nitride, lanthanum aluminate or hafnium aluminum oxide; The second dielectric layer (4) is made of at least one of oxide, nitride, high-dielectric-constant dielectric or oxide, nitride and oxide stack; the floating dielectric layer (3) is made of polysilicon or metal; The control grid layer (5) is made of polysilicon or metal; the insulating layer (8) is made of at least one of silicon dioxide, aluminum oxide or silicon oxynitride.

Description

Semiconductor device with engineering gate dielectric stack and preparation method thereof Technical Field The invention relates to the technical field of power semiconductor devices, in particular to a semiconductor device with an engineering grid dielectric stack and a preparation method thereof. Background Vertical metal-oxide-semiconductor field effect transistors (vertical MOSFETs) are unipolar power semiconductor devices in which voltage controlled current switching operates. The vertical MOSFET has a high impedance control terminal (gate) that adjusts the conductivity of the channel between the other two terminals (source and drain). When the gate voltage exceeds the threshold, a conductive path is formed, the channel resistance decreases, allowing a large current to flow, and the drain-to-source voltage is small. Conversely, when the gate voltage is below the threshold, the channel is non-conductive and has a high resistance, and the device can ignore the current blocking high drain-to-source voltage. Existing vertical MOSFETs, devices are built on semiconductor wafer substrates (e.g., silicon carbide, diamond, or gallium nitride). The source electrode is fabricated on the side and the drain electrode is at the bottom (back). An N-type drift layer is disposed between the drain and the source. The P-type base region is in direct contact with the source electrode. The n+ source is embedded in the P-type base region and contacts the source electrode through the contact opening. A gate electrode overlies the P-type base portion between the N-type drift region and the N + source, which defines the MOSFET channel, the gate electrode also extending over the N-type drift region, the gate electrode being electrically isolated from the semiconductor by a dielectric such as silicon dioxide. The material properties of the gate dielectric strongly shape the behavior of the MOSFET. In particular, when the oxide thickness is fixed, the transconductance (the amount of change in drain current given a change in gate voltage) increases approximately linearly with the dielectric constant of the dielectric. This is because the transconductance is proportional to the gate oxide capacitance, which increases as the permittivity increases. Physically, a higher dielectric constant dielectric allows the gate to pull more inversion charge into the channel at the same voltage, and thus more current. Thus, MOSFETs using high dielectric constant (high-k) gate dielectrics can provide higher channel conductivity and lower conduction (static) losses, which is one of the key advantages of high-k power MOSFETs. Channel conductivity depends not only on the dielectric constant of the gate dielectric, but also on channel geometry (width and length), carrier mobility, and threshold voltage. The threshold voltage is set by the semiconductor stack (e.g., doping, work function difference, and fixed or interfacial charge), also affected by the gate dielectric. In high-k power MOSFETs, a critical design task is to achieve low gate leakage current and threshold voltages suitable for applications while maintaining the higher transconductance provided by the large gate capacitance. Since the gate capacitance increases with increasing dielectric constant and decreases with increasing dielectric thickness, the use of higher dielectric constant materials or thinning of dielectric materials increases transconductance, but increases leakage and lowers the threshold. Thus, the threshold voltage of a vertical MOSFET optimized for high transconductance is typically too low for general applications and may even be normally on, which means that there is an inversion channel at zero gate bias. Charge storage within a gate dielectric stack is a well-established technique for trimming the threshold voltage of a MOSFET, particularly in non-volatile memory technology. Two prototype methods are widely used, 1, floating gate structures, a conductive floating gate (polysilicon and/or metal) disposed between two dielectric layers, a wide band gap, low dielectric constant material adjacent to the semiconductor, and a blocking (or coupling) dielectric under the control gate. Programming and erasing are accomplished by injecting charge into or removing charge from the floating gate, typically by Fowler-Nordheim tunneling or injecting hot carriers through a wide band gap, low dielectric constant material, while blocking dielectrics inhibit charge leakage to the control gate during normal operation. 2.A charge trap (ONO) stack. An oxide-nitride-oxide (ONO) stack replaces the discrete floating gates. The central nickel nitride layer acts as a charge storage medium (due to its trap states and band offset). The oxide at the semiconductor interface acts as a tunneling barrier for carrier injection/removal and the oxide towards the control gate acts as a blocking barrier limiting the charge loss of the gate electrode. The prior art has disclosed floating gate power MOSFET co