CN-122028480-A - Groove SiC JFET device structure of asymmetric grid and manufacturing method thereof

CN122028480ACN 122028480 ACN122028480 ACN 122028480ACN-122028480-A

Abstract

The invention discloses a groove SiC JFET device structure of an asymmetric grid and a manufacturing method thereof, wherein a mask is formed on a first conduction type source region material, and a groove, a first conduction type channel layer positioned in the groove and a first conduction type source region are formed by etching; the first conductive type channel layer is subjected to inclined ion implantation to form a second conductive type side wall gate region on the side wall, close to the second characteristic groove, of the first conductive type channel layer, the first conductive type channel layer is subjected to inclined ion implantation to form a first conductive type high doping channel on the side wall, close to the first characteristic groove, of the first conductive type channel layer, and the first conductive type high doping channel is communicated with the first conductive type source region and the first conductive type current expansion layer. According to the method, the high-doped conductive channel is accurately constructed in the channel region through ion implantation, and the manufacturing process controllability of the groove SiC JFET device is improved.

Inventors

YING XIANWEI
HUANG YU
BAI SONG
GUO CHEN
LI SHIYAN
HUANG RUNHUA
YANG YONG

Assignees

南京第三代半导体技术创新中心有限公司
中国电子科技集团公司第五十五研究所
南京第三代半导体技术创新中心

Dates

Publication Date: 20260512
Application Date: 20260414

Claims (10)

1. The manufacturing method of the groove SiC JFET device structure with the asymmetric grid is characterized by comprising the following steps of: step 1, sequentially growing and forming a first conductive type voltage-resistant layer, a first conductive type current expansion layer and a first conductive type channel layer material from bottom to top on a first conductive type substrate; Step 2, forming a first conduction type source region material on the first conduction type channel layer material; Step 3, forming a mask on the first conduction type source region material, and etching a first conduction type channel layer material, a first conduction type source region material forming groove, a first conduction type channel layer and a first conduction type source region which are positioned in the groove based on the mask, wherein the grooves on two sides of the first conduction type channel layer and the first conduction type source region are respectively a first characteristic groove and a second characteristic groove; step4, performing oblique ion implantation on the first conduction type channel layer to enable the first conduction type channel layer to form a second conduction type side wall gate region on the side wall close to the second characteristic groove; Step 5, forming a second conduction type bottom gate region on the surface of the first conduction type current expansion layer at the bottom of the groove through vertical ion implantation; step 6, performing inclined ion implantation on the first conductive type channel layer to enable the first conductive type channel layer to form a first conductive type high doping channel on the side wall of one side close to the first characteristic groove, wherein the first conductive type high doping channel is communicated with the first conductive type source region and the first conductive type current expansion layer, and the doping concentration of the first conductive type high doping channel is far higher than that of the first conductive type channel layer; Step 7, removing the mask to form dielectric side walls positioned on the side walls of the first characteristic groove and the second characteristic groove, wherein the dielectric side walls mask the first conductive type high doping channel and the second conductive type side wall gate region to expose the second conductive type bottom gate region and the first conductive type source region; step 8, forming source alloy at the top of the source region of the first conductivity type, forming gate alloy at the bottom of the trench and at the top of the gate region of the second conductivity type; Step 9, forming a passivation dielectric layer filling the groove; and 10, forming a source metal electrode on the passivation dielectric layer and the source alloy, and forming a drain metal electrode at the bottom of the first conductive type substrate.
2. The method of manufacturing an asymmetric gate trench SiC JFET device structure of claim 1 wherein the angle of the angled ion implantation in step 4 is in the range of 7-45, the implantation energy is in the range of 10KeV-500KeV, and the implantation dose is 5E12/cm 2 -1E14/cm 2 .
3. The method of manufacturing an asymmetric gate trench SiC JFET device structure of claim 1 wherein the angle of the angled ion implantation in step 6 is in the range of 7-45, the implantation energy is in the range of 50KeV-700KeV, and the implantation dose is 5E12/cm 2 -1E14/cm 2 .
4. The method of manufacturing an asymmetric gate trench SiC JFET device structure of claim 1, wherein the tilted ion implants in step 4 and step 6 are in the form of multiple implants.
5. The method of manufacturing an asymmetric gate trench SiC JFET device structure of claim 1, wherein the implantation energy of the vertical ion implantation in step 5 is greater than or equal to 30KeV, and the implantation dosage range is 1E13/cm 2 -1E15/cm 2 .
6. The method of claim 1 wherein the source metal electrode, the drain metal electrode, the gate alloy and the source alloy are one or more combinations of Ti, al, ni, pt, ag.
7. The method of manufacturing an asymmetric gate trench SiC JFET device structure of claim 1, wherein the passivation dielectric layer is made of silicon nitride, silicon oxide or a composite medium of silicon nitride and silicon oxide.
8. The method of manufacturing the asymmetric gate trench SiC JFET device structure of claim 1, wherein the first conductivity type voltage-resistant layer has a doping concentration range of 1e14cm -3 ~5e16cm -3 , the first conductivity type current spreading layer has a doping concentration range of 1e15cm -3 ~1e17cm -3 , the first conductivity type channel layer has a doping concentration range of 1e14cm -3 ~5e16cm -3 , and the first conductivity type source region has a doping concentration range of 1e17cm -3 ~ 1e19cm -3 .
9. The method of manufacturing an asymmetric gate trench SiC JFET device structure of claim 1, wherein the first conductivity type channel layer has a width in the range of 0.2 μm-2 μm.
10. An asymmetric gate trench SiC JFET device structure made by a method of fabricating an asymmetric gate trench SiC JFET device structure as claimed in any one of claims 1-9, comprising: The semiconductor device comprises a drain metal electrode, a first conductive type substrate, a first conductive type voltage-resistant layer, a first conductive type current expansion layer, a second conductive type current expansion layer, a first conductive type voltage-resistant layer, a second conductive type current expansion layer and a second conductive type current expansion layer, wherein the first conductive type voltage-resistant layer is arranged on the drain metal electrode; the semiconductor device comprises a first conductive type current expansion layer, a first conductive type channel layer, a first conductive type source region, a first conductive type channel layer, a first characteristic groove and a second characteristic groove, wherein the first conductive type channel layer is arranged on the first conductive type current expansion layer; a second conductivity type sidewall gate region located on a sidewall of the first conductivity type channel layer adjacent to the second feature trench; the second conduction type bottom gate region is positioned on the surface of the first conduction type current expansion layer, on two sides of the first conduction type channel layer and at the bottom of the groove; The first conductive type high doping channel is positioned on one side wall of the first conductive type channel layer close to the first characteristic groove and is connected with the first conductive type source region and the first conductive type current expansion layer; dielectric side walls positioned at two sides of the first conductive type channel layer; A gate alloy over the bottom gate region of the second conductivity type and at the bottom of the trench; A passivation dielectric layer positioned on the gate alloy and filling the trench; a source metal electrode located over the passivation dielectric layer and over the source alloy.

Description

Groove SiC JFET device structure of asymmetric grid and manufacturing method thereof Technical Field The invention relates to the technical field of power electronic devices, in particular to a groove SiC JFET device structure with an asymmetric grid and a manufacturing method thereof. Background The silicon carbide junction field effect transistor (Silicon Carbide Junction Field-Effect Transistor, siC JFET) has no gate oxide layer structure, high working temperature, small specific on-resistance and high reliability, and has obvious application value in the fields of solid-state circuit breakers, peak-shifting regulators, electronic fuses and the like. The groove type SiC JFET has the advantages of small cell size and high current density. As shown in fig. 1, in the structure of the prior art, the working principle of the conventional symmetric gate trench SiC JFET device is that when the gate-source voltage V GS is larger than or equal to the threshold voltage V (GS)TH, a channel is opened, current flows from a first conduction type channel layer, and when V GS is smaller than the threshold voltage V (GS)TH, the channel is closed. The conventional groove type SiC JFET device has the manufacturing process problems of groove etching precision control, including control of groove depth, groove width and groove angle. The device turn-on and turn-off characteristics are closely related to the trench size. For example, when the depth of the trench is shallow, the pinch-off effect of the trench is reduced, the reverse leakage current increases, and conversely, the on-resistance is deteriorated. Disclosure of Invention Aiming at the defect that the groove etching precision is difficult to control in the prior art, the invention provides the groove SiC JFET device structure of the asymmetric grid and the manufacturing method thereof, and the manufacturing process controllability of the groove SiC JFET device and the current density of the device are further improved by optimizing the device structure, namely precisely constructing a high-doped conductive channel in a channel region through ion implantation. The technical scheme is that the following technical scheme is adopted to achieve the technical purpose. A manufacturing method of a groove SiC JFET device structure with an asymmetric grid comprises the following steps: step 1, sequentially growing and forming a first conductive type voltage-resistant layer, a first conductive type current expansion layer and a first conductive type channel layer material from bottom to top on a first conductive type substrate; Step 2, forming a first conduction type source region material on the first conduction type channel layer material; Step 3, forming a mask on the first conduction type source region material, and etching a first conduction type channel layer material, a first conduction type source region material forming groove, a first conduction type channel layer and a first conduction type source region which are positioned in the groove based on the mask, wherein the grooves on two sides of the first conduction type channel layer and the first conduction type source region are respectively a first characteristic groove and a second characteristic groove; step4, performing oblique ion implantation on the first conduction type channel layer to enable the first conduction type channel layer to form a second conduction type side wall gate region on the side wall close to the second characteristic groove; Step 5, forming a second conduction type bottom gate region on the surface of the first conduction type current expansion layer at the bottom of the groove through vertical ion implantation; Step 6, performing inclined ion implantation on the first conductive type channel layer to enable the first conductive type channel layer to form a first conductive type high doping channel on the side wall of one side close to the first characteristic groove, wherein the first conductive type high doping channel is communicated with the first conductive type source region and the first conductive type current expansion layer; Step 7, removing the mask to form dielectric side walls positioned on the side walls of the first characteristic groove and the second characteristic groove, wherein the dielectric side walls mask the first conductive type high doping channel and the second conductive type side wall gate region to expose the second conductive type bottom gate region and the first conductive type source region; step 8, forming source alloy at the top of the source region of the first conductivity type, forming gate alloy at the bottom of the trench and at the top of the gate region of the second conductivity type; Step 9, forming a passivation dielectric layer filling the groove; and 10, forming a source metal electrode on the passivation dielectric layer and the source alloy, and forming a drain metal electrode at the bottom of the first conductive type substrate. Preferably