CN-122028483-A - Preparation method of semiconductor structure

CN122028483ACN 122028483 ACN122028483 ACN 122028483ACN-122028483-A

Abstract

The invention provides a preparation method of a semiconductor structure, which belongs to the field of semiconductors and comprises the steps of providing a substrate, forming a pseudo gate structure on the substrate, sequentially arranging an interface layer, a gate dielectric layer, a barrier layer and an oxide layer between the substrate and the pseudo gate structure, forming a contact hole etching stop layer on the pseudo gate structure and the substrate, forming an interlayer dielectric layer on the contact hole etching stop layer, flattening the interlayer dielectric layer and the contact hole etching stop layer until the pseudo gate structure is exposed, forming a doped layer on the pseudo gate structure, the interlayer dielectric layer and the contact hole etching stop layer, etching the doped layer on the pseudo gate structure, sequentially removing the pseudo gate structure and the oxide layer, forming a metal material layer on the barrier layer and the doped layer, flattening the metal material layer, the doped layer, the interlayer dielectric layer and the contact hole etching stop layer, and forming a metal gate on the barrier layer. By the preparation method provided by the invention, the aggravation of the dishing can be avoided, thereby avoiding the reduction of the height of the metal grid.

Inventors

ZHOU JI
ZHANG WEI
Su Shengzhe
Yun Guangtao
Shao Zhangpeng

Assignees

合肥晶合集成电路股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260327

Claims (10)

1. A method for fabricating a semiconductor structure, comprising at least the steps of: Providing a substrate, forming a plurality of dummy gate structures arranged at intervals on the substrate, and sequentially arranging an interface layer, a gate dielectric layer, a barrier layer and an oxide layer between the substrate and the dummy gate structures; Forming a contact hole etching stop layer on the pseudo gate structure and the substrate; Forming an interlayer dielectric layer on the contact hole etching stop layer; Flattening the interlayer dielectric layer and the contact hole etching stop layer until the dummy gate structure is exposed, wherein the surface of the interlayer dielectric layer is lower than the surface of the dummy gate structure to form a dishing recess; Forming a doped layer on the pseudo gate structure, the interlayer dielectric layer and the contact hole etching stop layer, and sequentially removing the pseudo gate structure and the oxide layer after etching the doped layer on the pseudo gate structure, wherein the rest part of the doped layer on the interlayer dielectric layer; forming a metal material layer on the barrier layer and the doped layer, and And flattening the metal material layer, the doped layer, the interlayer dielectric layer and the contact hole etching stop layer, and forming a metal gate on the barrier layer.
2. The method of claim 1, wherein the doping layer is deposited on the dummy gate structure, the interlayer dielectric layer and the contact etch stop layer by plasma enhanced chemical vapor deposition using methyldiethoxysilane as a precursor.
3. The method of claim 2, wherein the precursor flow is 2g/min to 10g/min, the deposition temperature is 150 ℃ to 400 ℃, the deposition pressure is 1Torr to 10Torr, and the deposition time is 2s to 10s.
4. The method of claim 1, wherein the thickness of the doped layer on the interlayer dielectric layer is greater than the thickness of the doped layer on the dummy gate structure.
5. The method of claim 4, wherein the doped layer on the interlayer dielectric layer has a thickness of 100 a-150 a and the doped layer on the dummy gate structure has a thickness of 80 a-140 a.
6. The method of claim 1, wherein the doped layer has a chemical formula of [ SiO x (CH 3 ) y H z ] n ] wherein 0< x+y+z≤ 4,0.5≤x≤ 2.5,0.5≤y≤2.0, 0≤z≤1.5, and n is a positive integer.
7. The method of claim 1, wherein the oxide layer is removed by wet etching, and the etching rate of the etching solution on the oxide layer is greater than the etching rate of the doped layer.
8. The method according to claim 7, wherein the etching solution is hydrofluoric acid or a mixed solution of hydrofluoric acid and ammonium fluoride.
9. The method of claim 1, wherein the thickness of the doped layer on the interlayer dielectric layer is reduced after the oxide layer is removed.
10. The method of claim 9, wherein the doped layer on the interlayer dielectric layer has a thickness of 50 a-100 a after thinning.

Description

Preparation method of semiconductor structure Technical Field The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure. Background In the dummy gate removal process, in order to achieve gap filling and surface planarization between the dummy gates, a high aspect ratio process is commonly used in the industry to deposit a silicon dioxide layer as a gap filling medium, and then a Chemical Mechanical Polishing (CMP) process is used to planarize the silicon dioxide and the dummy gates. However, since the polishing rates of the polishing liquid on the silicon dioxide, the silicon nitride and the polysilicon are significantly different, dishing is easy to generate on the surface of the silicon dioxide layer in the planarization process, dishing is further deteriorated in the subsequent process steps, causing a series of linkage adverse effects, specifically, when the oxide layer formed between the polysilicon and the titanium nitride layer is removed, hydrofluoric acid is usually used for etching treatment, and is inevitably contacted with the silicon dioxide layer, the etching effect of the hydrofluoric acid on the silicon dioxide layer can further deepen and enlarge the dishing formed on the silicon dioxide layer, so that after the subsequent metal gate preparation process, the dishing concave area inevitably deposits metal materials to form metal residues, and in order to remove the metal residues, the polishing treatment is additionally performed, thereby causing the height reduction of the metal gate, damaging the structural integrity of the device, and finally significantly reducing the yield of the semiconductor device. Disclosure of Invention The invention provides a preparation method of a semiconductor structure, which can avoid the aggravation of dishing, thereby avoiding the reduction of the height of a metal grid and improving the yield of semiconductor devices. In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, at least comprising the following steps: Providing a substrate, forming a plurality of dummy gate structures arranged at intervals on the substrate, and sequentially arranging an interface layer, a gate dielectric layer, a barrier layer and an oxide layer between the substrate and the dummy gate structures; Forming a contact hole etching stop layer on the pseudo gate structure and the substrate; Forming an interlayer dielectric layer on the contact hole etching stop layer; Flattening the interlayer dielectric layer and the contact hole etching stop layer until the dummy gate structure is exposed, wherein the surface of the interlayer dielectric layer is lower than the surface of the dummy gate structure to form a dishing recess; Forming a doped layer on the pseudo gate structure, the interlayer dielectric layer and the contact hole etching stop layer, and sequentially removing the pseudo gate structure and the oxide layer after etching the doped layer on the pseudo gate structure, wherein the rest part of the doped layer on the interlayer dielectric layer; forming a metal material layer on the barrier layer and the doped layer, and And flattening the metal material layer, the doped layer, the interlayer dielectric layer and the contact hole etching stop layer, and forming a metal gate on the barrier layer. In an embodiment of the present invention, when the doped layer is formed, methyldiethoxysilane is used as a precursor, and the doped layer is deposited on the dummy gate structure, the interlayer dielectric layer and the contact hole etching stop layer by a plasma enhanced chemical vapor deposition method. In one embodiment of the invention, the precursor flow is 2g/min-10g/min, the deposition temperature is 150 ℃ to 400 ℃, the deposition pressure is 1Torr-10Torr, and the deposition time is 2s-10s. In an embodiment of the present invention, a thickness of the doped layer on the interlayer dielectric layer is greater than a thickness of the doped layer on the dummy gate structure. In an embodiment of the present invention, the thickness of the doped layer on the interlayer dielectric layer is 100 a-150 a, and the thickness of the doped layer on the dummy gate structure is 80 a-140 a. In one embodiment of the invention, the chemical formula of the material of the doped layer is [ SiO x(CH3)yHz]n ], wherein 0< x+y+z is equal to or less than 4,0.5 and equal to or less than 2.5,0.5 and equal to or less than y and equal to or less than 2.0,0 and equal to or less than z and equal to or less than 1.5, and n is a positive integer. In an embodiment of the present invention, a wet etching method is used when the oxide layer is removed, and an etching rate of the etching solution on the oxide layer is greater than an etching rate of the doped layer. In an embodiment of the present invention, the etching solution is hydrofluoric acid or a mixed solu