CN-122028484-A - Semiconductor device and method for manufacturing the same

Abstract

The invention discloses a semiconductor element, which comprises a substrate, a semiconductor channel layer, a semiconductor barrier layer, a source electrode, a gate electrode and a drain stack layer. The drain stack layer comprises a first drain layer comprising a first body portion and a first extension portion, and the bottom surface of the first extension portion is higher than the top surface of the first body portion. The second drain electrode layer is arranged on the first drain electrode layer and comprises a second body part and a second extension part, wherein the length of the second drain electrode layer is larger than that of the first drain electrode layer in the first direction, and the top surface of the second extension part is higher than that of the second body part. The third drain electrode layer is arranged on the second drain electrode layer and comprises a third body part and a third extension part. The invention also discloses a manufacturing method of the semiconductor element.

Inventors

• Xie Tingen
• LIAN YIWEI
• CAI XINCHANG
• ZHENG WEIZHI

Assignees

• 世界先进积体电路股份有限公司

Dates

Publication Date

20260512

Application Date

20241104

Claims (18)

1. 1. A semiconductor element, characterized by comprising: A substrate; A semiconductor channel layer and a semiconductor barrier layer disposed on the substrate; a gate electrode disposed on the semiconductor barrier layer; A first interlayer dielectric layer disposed on the semiconductor barrier layer and the gate electrode; A source electrode arranged on one side of the gate electrode, and A drain stack layer disposed on the other side of the gate electrode and laterally separated from the gate electrode, the drain stack layer comprising: the first drain electrode layer comprises a first body part and a first extension part, the first extension part covers the first interlayer dielectric layer, and the bottom surface of the first extension part is higher than the top surface of the first body part; A second drain layer disposed on the first drain layer and including a second body portion and a second extension portion covering the first extension portion, wherein in a first direction, the second drain layer has a length greater than that of the first drain layer and the top surface of the second extension portion is higher than that of the second body portion, and And a third drain layer disposed on the second drain layer and including a third body portion and a third extension portion.
2. 2. The semiconductor device of claim 1, further comprising a drain opening disposed in the first interlayer dielectric layer, and the first body portion is disposed within the drain opening.
3. 3. The semiconductor device of claim 1, wherein the top surface of the second extension comprises a rounded top surface.
4. 4. The semiconductor device of claim 3, wherein the rounded top surface is directly above the first extension.
5. 5. The semiconductor device of claim 1, wherein the second extension extends beyond a distal edge of the first extension.
6. 6. The semiconductor element according to claim 1, further comprising: And the second interlayer dielectric layer is arranged between the first extension part and the second extension part and covers the top surface of the first body part.
7. 7. The semiconductor device of claim 6, wherein a portion of the second interlayer dielectric layer is located within the drain opening.
8. 8. The semiconductor device according to claim 6, wherein the second interlayer dielectric layer comprises a raised region, and wherein an apex of the raised region is higher than a bottom surface of the second extension.
9. 9. The semiconductor device of claim 1, wherein a length of the third drain layer is smaller than a length of the first drain layer in the first direction, and the third extension is laterally separated from the first interlayer dielectric layer.
10. 10. The semiconductor device of claim 1, wherein a length of the third drain layer is greater than a length of the second drain layer in the first direction, and the third extension covers and passes over the second extension.
11. 11. The semiconductor device according to claim 10, wherein the third extension portion includes a circular top surface, and the circular top surface is located directly above the first extension portion.
12. 12. The semiconductor device of claim 1, wherein a length of the second extension in the first direction is 5% -30% of a distance between the drain structure and the gate electrode.
13. 13. The semiconductor device of claim 1, further comprising an inter-layer metal dielectric layer disposed on the third drain layer, wherein the inter-layer metal dielectric layer comprises at least one void, and wherein a maximum length of the at least one void is less than 5nm in a cross-sectional view.
14. 14. A method of manufacturing a semiconductor device, comprising: Providing a substrate, wherein the substrate comprises a substrate, a semiconductor channel layer and a semiconductor barrier layer from bottom to top in sequence; Forming a gate electrode on the bottom dielectric layer; forming a first interlayer dielectric layer to cover the gate electrode; Forming a source electrode on one side of the gate electrode; forming a first drain layer on the other side of the gate electrode, wherein the first drain layer comprises a first body portion and a first extension portion covering a part of the first interlayer dielectric layer, and Forming a second drain layer on the first drain layer, wherein the second drain layer comprises a second body portion and a second extension portion, and the second extension portion covers the second interlayer dielectric layer, wherein in a first direction, the length of the second drain layer is greater than the length of the first drain layer, and the top surface of the second extension portion is higher than the top surface of the second body portion.
15. 15. The method of manufacturing a semiconductor device according to claim 14, further comprising, after forming the second drain layer: Forming a third interlayer dielectric layer covering the second extension and the second interlayer dielectric layer, and Forming a third drain layer on the second drain layer, wherein the third drain layer comprises a third body portion and a third extension portion.
16. 16. The method of manufacturing a semiconductor device according to claim 14, further comprising, before forming the gate electrode: A bottom dielectric layer is formed on the semiconductor barrier layer, wherein the bottom dielectric layer includes a gate opening therein, and the gate electrode is located in the gate opening.
17. 17. The method of manufacturing a semiconductor device according to claim 14, wherein a length of the third drain layer in the first direction is less than or equal to a length of the second drain layer, and the third extension portion covers a portion of the second extension portion.
18. 18. The method of claim 14, wherein a length of the third drain layer is greater than a length of the second drain layer in the first direction, and the third extension covers and extends beyond an end edge of the second extension.

Description

Semiconductor device and method for manufacturing the same Technical Field The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for receiving a high voltage and a method of manufacturing the same. Background In semiconductor technology, III-V semiconductor compounds are used in a variety of integrated circuit devices, such as high power field effect transistors, high frequency transistors, or high electron mobility transistors (high electron mobility transistor, HEMTs). HEMTs are a type of transistor with two-dimensional electron gas (two-dimensional electron gas,2 DEG) that is adjacent to the junction between two materials with different energy gaps (i.e., the heterojunction). Because HEMTs do not use doped regions as the carrier channel of the transistor, but rather use 2DEG as the carrier channel of the transistor, HEMTs have a variety of attractive characteristics, such as high electron mobility and the ability to transmit signals at high frequencies, compared to existing Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). For an existing HEMT, it may include a compound semiconductor channel layer, a compound semiconductor barrier layer, a compound semiconductor cap layer, and a gate electrode stacked in order. The grid electrode is utilized to apply bias to the compound semiconductor cover layer, so that the two-dimensional electron gas concentration in the compound semiconductor channel layer below the compound semiconductor cover layer can be regulated, and further the switching of the HEMT can be regulated. In addition, a field plate is further disposed in the conventional HEMT to regulate electric field distribution through the field plate, thereby increasing breakdown voltage of the HEMT. However, when a field plate is provided in a HEMT, since the field plate generally has a rugged topography, the topography tends to cause structural defects in the interlayer dielectric layer adjacent to the field plate, thereby reducing the withstand voltage capability of the HEMT. Disclosure of Invention In view of the foregoing, there is a need for an improved semiconductor device and a method for manufacturing the same that overcomes the drawbacks of the conventional semiconductor devices. According to one embodiment of the invention, a semiconductor element is provided, which comprises a substrate, a semiconductor channel layer and a semiconductor barrier layer, a gate electrode, a first interlayer dielectric layer, a source electrode and a drain stack layer, wherein the semiconductor channel layer and the semiconductor barrier layer are arranged on the substrate, the gate electrode is arranged on the semiconductor barrier layer, the first interlayer dielectric layer is arranged on the semiconductor barrier layer and the gate electrode, the source electrode is arranged on one side of the gate electrode, the drain stack layer is arranged on the other side of the gate electrode and is laterally separated from the gate electrode, the drain stack layer comprises a first drain layer, the first drain layer comprises a first body part and a first extension part, the first extension part covers the first interlayer dielectric layer, the bottom surface of the first extension part is higher than the top surface of the first body part, the second drain layer is arranged on the first drain layer and comprises a second body part and a second extension part, the second extension part covers the second interlayer dielectric layer, the length of the second drain layer is longer than the length of the first drain layer, the top surface of the second extension part is higher than the top surface of the second body part, and the third drain layer is arranged on the second drain layer and comprises the third extension part and the third extension part. According to other embodiments of the present invention, a method for manufacturing a semiconductor device is provided, which includes providing a substrate including a substrate, a semiconductor channel layer and a semiconductor barrier layer in order from bottom to top, forming a gate electrode on the semiconductor barrier layer, forming a first interlayer dielectric layer covering the gate electrode, forming a source electrode on one side of the gate electrode, forming a first drain layer on the other side of the gate electrode, wherein the first drain layer includes a first body portion and a first extension portion, and the first extension portion covers a portion of the first interlayer dielectric layer, and forming a second drain layer on the first drain layer, wherein the second drain layer includes a second body portion and a second extension portion, and the second extension portion covers the second interlayer dielectric layer, wherein a length of the second drain layer is greater than a length of the first drain layer in a first direction, and a top surface of the second extension portion is higher than a