CN-122028485-A - Chip package, manufacturing method thereof and electronic equipment

CN122028485ACN 122028485 ACN122028485 ACN 122028485ACN-122028485-A

Abstract

The application provides a chip package, a manufacturing method thereof and electronic equipment. The chip package comprises a first chip layer and a second chip layer, wherein the first chip layer comprises at least two chips which are arranged at intervals along the layer surface direction, an isolation groove is arranged between every two adjacent chips in the first chip layer, the isolation groove penetrates through the first chip layer and the middle bonding pad layer in the thickness direction of the first chip layer, the isolation groove comprises a first groove body and a second groove body in the thickness direction of the first chip layer, the first groove body is arranged close to the second chip layer, the second groove body is arranged away from the second chip layer, and the width of the first groove body is smaller than that of the second groove body along the arrangement direction of every two adjacent chips. The front cutting gap of the chip packaging body is small, and the effective utilization rate of the chip can be improved.

Inventors

REN NANA
LIU SIYAN
WU SHENGHAO
LI XIAORU
HUANG YULIN
CHEN TAO
YU ZIBIN
ZHANG TONGLONG

Assignees

华为技术有限公司

Dates

Publication Date: 20260512
Application Date: 20241106

Claims (10)

1. The chip package is characterized by comprising a first chip layer and a second chip layer, wherein the first chip layer is stacked on one side of the second chip layer and is connected with the second chip layer through an intermediate bonding pad layer, the thickness of the first chip layer is more than or equal to 200 mu m, and the thickness of the second chip layer is less than 200 mu m; The first chip layer comprises at least two chips which are arranged at intervals along the layer surface direction, and an isolation groove is arranged between two adjacent chips in the first chip layer; The isolation groove comprises a first groove body and a second groove body in the thickness direction of the first chip layer, the first groove body is arranged close to the second chip layer, the second groove body is arranged away from the second chip layer, and the width of the first groove body is smaller than that of the second groove body along the arrangement direction of two adjacent chips.
2. The chip package of claim 1, wherein the isolation trench is filled with an organic insulating material.
3. The chip package according to claim 1 or 2, wherein an edge of the first chip layer is provided with a plastic package.
4. The chip package of claim 3, wherein the plastic package has a ring-shaped structure along a layer direction of the first chip layer.
5. The chip package according to claim 3 or 4, wherein the plastic package has a stepped structure along a thickness direction of the first chip layer, and a thickness of an end of the plastic package close to the second chip layer is smaller than a thickness of an end of the plastic package far from the second chip layer.
6. The chip package of any of claims 1-5, wherein the second chip layer is at least one layer, each layer of the second chip layer comprising at least one chip.
7. A method of fabricating a chip package, comprising: etching the front surface of a first wafer to form a first groove body, wherein the first wafer comprises a device functional layer arranged on the front surface of the first wafer and a substrate layer arranged on the back surface of the first wafer, an intermediate bonding pad layer is arranged on the surface of the device functional layer, and the first groove body penetrates through the intermediate bonding pad layer and the device functional layer along the thickness direction of the first wafer; Bonding the middle bonding pad layer with an auxiliary supporting piece, mechanically cutting the back surface of the first wafer to form a second groove body, enabling the second groove body to penetrate through the first groove body to form an isolation groove, wherein the width of the first groove body is smaller than that of the second groove body; And separating the auxiliary supporting piece, attaching the first chip layer to the surface of the second wafer, and thinning one side, away from the first chip layer, of the second wafer to form a second chip layer, wherein the thickness of the second chip layer is smaller than 200 mu m, and the surface, provided with the middle bonding pad layer, of the first chip layer is connected with the second wafer in a bonding way.
8. The method of manufacturing a chip package according to claim 7, wherein after separating the auxiliary support member and before attaching the first chip layer to the surface of the second wafer, the method further comprises filling an organic insulating material in the isolation trench and molding an edge of the first chip layer.
9. The method of manufacturing a chip package according to claim 7 or 8, wherein after forming the second chip layer, the method of manufacturing a chip package further comprises manufacturing a wiring layer and a bottom pad layer on a back surface of the second chip layer.
10. An electronic device comprising a chip package according to any one of claims 1-6.

Description

Chip package, manufacturing method thereof and electronic equipment Technical Field The application relates to the field of chip packaging, in particular to a chip packaging body, a manufacturing method thereof and electronic equipment. Background As chip manufacturing processes approach physical size limits, three-dimensional (3D) stacked packaging technology has become an important technological route for improving chip integration and performance. As the pitch of the chip interconnect pins in the 3D stacked package is reduced to below 10 microns, conventional micro bump (uBump) processes have failed to meet the requirements. Hybrid Bonding (HB) process, i.e., smaller size planar copper pads, is becoming one of the key technologies for three-dimensional stacked packaging and architectural design. In HB technology, the segmentation of the chip is particularly important. HB typically uses plasma etching for chip dicing to achieve better quality edge dicing quality. However, the efficiency of plasma dicing is low, and for chips with a thickness exceeding 200 μm, the working time will be more than one hour, resulting in high process costs. Therefore, for chips having a thickness exceeding 200 μm, dicing is often performed by mechanical dicing. However, mechanical cutting, such as cutting wheel cutting, has the problems of large cutting gap and poor cutting boundary quality in the cutting process. Under the condition that the minimum cutting width is limited, mechanical cutting can reduce the effective area of the front surface of the chip generally, and the utilization rate of the chip is reduced. Disclosure of Invention The application provides a chip package, a manufacturing method thereof and electronic equipment, which are used for reducing cutting gaps on the front surface of a chip and improving the effective utilization rate of the chip. The application provides a chip package body, which comprises a first chip layer and a second chip layer, wherein the first chip layer is stacked on one side of the second chip layer and is connected with the second chip layer through an intermediate bonding pad layer, the thickness of the first chip layer is more than or equal to 200 mu m, and the thickness of the second chip layer is less than 200 mu m; The isolation groove comprises a first groove body and a second groove body in the thickness direction of the first chip layer, the first groove body is arranged close to the second chip layer, the second groove body is arranged away from the second chip layer, and the width of the first groove body is smaller than that of the second groove body along the arrangement direction of two adjacent chips. The chip sealing member of the application can comprise a plurality of chip layers, such as a first chip layer and a second chip layer, which are stacked. Wherein the first chip layer is a thick chip layer with a thickness of 200 μm or more, and the second chip layer is a thin chip layer with a thickness of less than 200 μm. The first chip layer can comprise a plurality of chips arranged at intervals, the isolation grooves between the chips are of a ladder-shaped structure, the width dimension of one end close to the second chip layer is smaller, the width of one end far away from the second chip layer is larger, wherein one end of the first chip layer close to the second chip layer is the front surface of the chip and contains a device functional layer, the size of the isolation groove in the area is smaller, the cutting gap can be reduced, and the effective area of the chip is increased. And one end of the first chip layer, which is far away from the second chip layer, is a nonfunctional area, and the width between the second groove bodies corresponding to the nonfunctional area is large, so that the processing is convenient, and the processing efficiency is improved. In an alternative implementation, the isolation trenches are filled with an organic insulating material. The sealing of the side surfaces of the chips can be realized by filling the organic insulating material, and the insulativity between the chips is improved. In an alternative implementation, the edge of the first chip layer is provided with a plastic package. The edge of the first chip layer is sealed by arranging the plastic package part, so that the first chip layer is protected from being corroded by water vapor. In an alternative implementation manner, the plastic package is in an annular structure along the layer direction of the first chip layer, so as to realize better sealing protection on the periphery of the first chip layer. In an alternative implementation manner, the plastic package is in a stepped structure along the thickness direction of the first chip layer, and the thickness of one end of the plastic package, which is close to the second chip layer, is smaller than the thickness of one end of the plastic package, which is far away from the second chip layer. The size of one end close t