CN-122028487-A - Semiconductor package

Abstract

A semiconductor package includes a coreless circuit substrate including an insulating member having a plurality of insulating layers and a plurality of cavities, and a plurality of wiring layers respectively disposed on the plurality of insulating layers, a semiconductor chip disposed on an upper surface of the coreless circuit substrate and electrically connected to an uppermost wiring layer of the plurality of wiring layers, and a plurality of semiconductor-based chip capacitors respectively disposed in the plurality of cavities, and each of the semiconductor-based chip capacitors having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to a first wiring layer of the plurality of wiring layers adjacent to the first pad by a conductive bump, and the second pad is connected to an interconnect feedthrough of a second wiring layer of the plurality of wiring layers adjacent to the second pad.

Inventors

• Xin Yuanbin

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20251023

Priority Date

20241112

Claims (20)

1. 1. A semiconductor package, comprising: A coreless circuit substrate comprising an insulating member having a plurality of insulating layers and a plurality of cavities, and a plurality of wiring layers disposed on the plurality of insulating layers, respectively, and having interconnect vias connected to adjacent wiring layers; At least one semiconductor chip disposed on the upper surface of the coreless circuit substrate and electrically connected to the uppermost wiring layer of the plurality of wiring layers, and A plurality of semiconductor-based chip capacitors disposed in the plurality of cavities, respectively, and each of the plurality of semiconductor-based chip capacitors having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed, Wherein the first pad is connected to a first wiring layer of the plurality of wiring layers adjacent to the first pad by a conductive bump, and the second pad is connected to an interconnect feedthrough of a second wiring layer of the plurality of wiring layers adjacent to the second pad.
2. 2. The semiconductor package of claim 1, wherein the uppermost wiring layer includes a planar pattern for pads corresponding to chip pads of the at least one semiconductor chip.
3. 3. The semiconductor package according to claim 2, Wherein the first wiring layer is provided as the uppermost wiring layer, and Wherein the first pads of the plurality of semiconductor-based chip capacitors are respectively connected to lower surfaces of the planar patterns for pads.
4. 4. The semiconductor package of claim 1, wherein each of the plurality of semiconductor-based chip capacitors comprises: a semiconductor body having a first surface facing an upper surface of the coreless circuit substrate and a second surface positioned opposite the first surface, A capacitor structure having a first electrode and a second electrode on the first surface of the semiconductor body and a dielectric layer between the first electrode and the second electrode, A redistribution structure having a redistribution layer on the capacitor structure connected to the first and second electrodes, and And a through electrode penetrating the semiconductor body and connected to the second electrode.
5. 5. The semiconductor package according to claim 4, Wherein the capacitor structure comprises a base insulating layer disposed on the first surface of the semiconductor body and having a plurality of trenches, an Wherein the first and second electrodes and the dielectric layer are disposed along surfaces within the plurality of trenches.
6. 6. The semiconductor package according to claim 4, Wherein the first pad is electrically connected to the first electrode through the redistribution layer on the redistribution structure, and Wherein the second pad is electrically connected to the second electrode through the through electrode on the second surface of the semiconductor body.
7. 7. The semiconductor package of claim 1, wherein the interconnect feedthrough of the plurality of wiring layers has a width that narrows toward an upper surface of the coreless circuit substrate.
8. 8. The semiconductor package of claim 1, wherein each of the plurality of cavities has a depth corresponding to a thickness of one to four of the plurality of insulating layers.
9. 9. The semiconductor package according to claim 1, Wherein each of the plurality of cavities has an opening facing a lower surface of the coreless circuit substrate, and Wherein an insulating layer of the plurality of insulating layers, in which the second wiring layer is provided, fills at least a part of the plurality of cavities.
10. 10. The semiconductor package of claim 1, wherein the plurality of semiconductor-based chip capacitors comprises a first chip capacitor located at a first level of the coreless circuit substrate and a second chip capacitor located at a second level of the coreless circuit substrate that is lower than the first level.
11. 11. The semiconductor package of claim 10, wherein at least some of the first chip capacitors are arranged so as not to overlap the second chip capacitors in a thickness direction of the coreless circuit substrate.
12. 12. The semiconductor package according to claim 1, Wherein the at least one semiconductor chip comprises a first semiconductor chip and a second semiconductor chip, Wherein the semiconductor package further includes a semiconductor bridge embedded in the coreless circuit substrate and having an interconnect wiring layer electrically connecting the first semiconductor chip and the second semiconductor chip.
13. 13. The semiconductor package according to claim 12, wherein at least a portion of each of the plurality of semiconductor-based chip capacitors is disposed so as not to overlap the semiconductor bridge in a thickness direction of the coreless circuit substrate.
14. 14. A semiconductor package, comprising: A coreless circuit substrate including an insulating member having a plurality of insulating layers and a plurality of wiring layers respectively provided on the plurality of insulating layers, an uppermost wiring layer of the plurality of wiring layers including a planar pattern for a pad, and each of the plurality of wiring layers other than the uppermost wiring layer having an interconnection feedthrough connected to another adjacent wiring layer; A semiconductor chip disposed on the upper surface of the coreless circuit substrate and electrically connected to the planar pattern for pads of the uppermost wiring layer, and A plurality of semiconductor-based chip capacitors embedded in the coreless circuit substrate, and each of the plurality of semiconductor-based chip capacitors having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed, Wherein the first pad is connected to a lower surface of the plane pattern for a pad of the uppermost wiring layer, and the second pad is connected to an interconnection feedthrough of a wiring layer adjacent to the second pad among the plurality of wiring layers.
15. 15. The semiconductor package of claim 14, wherein the interconnect feedthrough of the plurality of wiring layers has a width that narrows toward an upper surface of the coreless circuit substrate.
16. 16. The semiconductor package of claim 14, wherein the plurality of insulating layers comprise the same insulating material.
17. 17. The semiconductor package of claim 14, wherein each of the plurality of semiconductor-based chip capacitors has a thickness in a range of 20 μιη to 70 μιη.
18. 18. A semiconductor package, comprising: A coreless circuit substrate including an insulating member having a plurality of insulating layers and a plurality of wiring layers respectively provided on the plurality of insulating layers, an uppermost wiring layer of the plurality of wiring layers including a planar pattern for a pad, and each of the plurality of wiring layers other than the uppermost wiring layer having an interconnection feedthrough connected to another adjacent wiring layer; a plurality of semiconductor chips disposed on an upper surface of the coreless circuit substrate and electrically connected to the planar pattern for pads of the uppermost wiring layer; A semiconductor bridge embedded in the coreless circuit substrate and having an interconnection wiring layer electrically connecting the plurality of semiconductor chips, and A plurality of semiconductor-based chip capacitors embedded in the coreless circuit substrate and having an upper surface on which the first pads are disposed and a lower surface on which the second pads are disposed, Wherein the first pad is connected to a first wiring layer of the plurality of wiring layers adjacent to the first pad through a first conductive bump, and the second pad is connected to an interconnect feedthrough of a second wiring layer of the plurality of wiring layers adjacent to the second pad.
19. 19. The semiconductor package according to claim 18, Wherein the semiconductor bridge includes a connection pad on the interconnect wiring layer, and Wherein the connection pads are respectively connected to the lower surfaces of the planar patterns for pads through second conductive bumps.
20. 20. The semiconductor package of claim 18, wherein at least some of the plurality of semiconductor-based chip capacitors are arranged so as not to overlap the semiconductor bridge in a thickness direction of the coreless circuit substrate.

Description

Semiconductor package Cross Reference to Related Applications The present application claims the benefit of korean patent application No.10-2024-0159921, filed on the 11 th month 12 of 2024, to the korean intellectual property office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field The present inventive concept relates to a semiconductor package. Background As electronic devices become lighter and more powerful, the field of semiconductor packaging also requires the development of miniaturized and high-performance semiconductor packages. In order to achieve miniaturization and high performance of semiconductor packages, packaging techniques in which passive components are embedded in a circuit board are continuously being developed. Disclosure of Invention Example embodiments provide a semiconductor package having a circuit board with passive components embedded therein. According to an example embodiment, a semiconductor package includes a coreless circuit substrate including an insulating member having a plurality of insulating layers and a plurality of cavities, and a plurality of wiring layers respectively disposed on the plurality of insulating layers and having interconnection vias connected to adjacent wiring layers, at least one semiconductor chip disposed on an upper surface of the coreless circuit substrate and electrically connected to an uppermost wiring layer of the plurality of wiring layers, and a plurality of semiconductor-based chip capacitors respectively disposed in the plurality of cavities, and each of the semiconductor-based chip capacitors having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to a first wiring layer of the plurality of wiring layers adjacent to the first pad by a conductive bump, and the second pad is connected to an interconnect feedthrough of a second wiring layer of the plurality of wiring layers adjacent to the second pad. According to an example embodiment, a semiconductor package includes a coreless circuit substrate including an insulating member having a plurality of insulating layers and a plurality of wiring layers respectively disposed on the plurality of insulating layers, an uppermost wiring layer of the plurality of wiring layers including a planar pattern for a pad, and each of the plurality of wiring layers except for the uppermost wiring layer having an interconnection feedthrough connected to another adjacent wiring layer, a semiconductor chip disposed on an upper surface of the coreless circuit substrate and electrically connected to the planar pattern for the pad of the uppermost wiring layer, and a plurality of semiconductor-based chip capacitors embedded in the coreless circuit substrate and having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to a lower surface of the uppermost wiring layer for the planar pattern of the pad, and the second pad is connected to an interconnection feedthrough of a wiring layer adjacent to the second pad among the plurality of wiring layers. According to an example embodiment, a semiconductor package includes a coreless circuit substrate including an insulating member having a plurality of insulating layers and a plurality of wiring layers respectively disposed on the plurality of insulating layers, an uppermost wiring layer of the plurality of wiring layers including a planar pattern for a pad, and each of the plurality of wiring layers having an interconnect feedthrough connected to another adjacent wiring layer except for the uppermost wiring layer, a plurality of semiconductor chips disposed on an upper surface of the coreless circuit substrate and electrically connected to the planar pattern for the pad of the uppermost wiring layer, a semiconductor bridge embedded in the coreless circuit substrate and having an interconnect wiring layer electrically connected to the plurality of semiconductor chips, and a plurality of semiconductor-based chip capacitors embedded in the coreless circuit substrate and having an upper surface on which a first pad is disposed and a lower surface on which a second pad is disposed. The first pad is connected to a first wiring layer of the plurality of wiring layers adjacent to the first pad through a first conductive bump, and the second pad is connected to an interconnect feedthrough of a second wiring layer of the plurality of wiring layers adjacent to the second pad. According to an example embodiment, a semiconductor-based chip capacitor includes a semiconductor body having a first surface and a second surface positioned opposite each other, a capacitor structure disposed on the first surface of the semiconductor body and having first and second electrodes and a dielectric layer between the first and second electrodes, a redistribution structure disposed on t