CN-122028490-A - Semiconductor structure and forming method thereof

Abstract

The invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a plurality of stacked structures on the substrate, wherein the stacked structures comprise a first channel structure located on the substrate and a second channel structure located on the first channel structure, filling a first source drain doping layer on the substrate between the stacked structures, wherein the first source drain doping layer covers the side face of the first channel structure, forming a first dielectric layer on the first source drain doping layer, and filling a second source drain doping layer on the first dielectric layer, and the second source drain doping layer covers the side face of the second channel structure. By adopting the technical scheme, the first source-drain doped layer and the second source-drain doped layer can be electrically isolated through the first dielectric layer, the leakage current between the first source-drain doped layer and the second source-drain doped layer is reduced, and the switching current ratio of the semiconductor structure is improved, so that the performance of the semiconductor structure can be optimized.

Inventors

• JIN SHA

Assignees

• 中芯国际集成电路制造(上海)有限公司

Dates

Publication Date

20260512

Application Date

20241112

Claims (16)

1. 1. A method of forming a semiconductor structure, comprising: providing a substrate; forming a plurality of stacked structures on the substrate, the stacked structures including a first channel structure on the substrate and a second channel structure on the first channel structure; Filling a first source-drain doping layer on the substrate between the stacked structure structures, wherein the first source-drain doping layer covers the side face of the first channel structure; forming a first dielectric layer on the first source-drain doping layer; and filling a second source-drain doping layer on the first dielectric layer, wherein the second source-drain doping layer covers the side face of the second channel structure.
2. 2. The method of forming of claim 1, wherein prior to filling the first source drain doped layer, the method further comprises: And a protective layer is covered on the side surface of the second channel structure in a conformal manner.
3. 3. The method of forming of claim 2, wherein the step of conformally covering the protective layer comprises: filling a space occupying layer on the substrate between the stacking junctions, wherein the space occupying layer covers the side wall of the first channel structure; covering a protective material layer on the side surface of the second channel structure and the top surface of the space occupying layer in a conformal manner; and removing the protective material layer at the top surface of the occupying layer, and using the protective material layer reserved at the side surface of the second channel structure as a protective layer.
4. 4. The method of forming of claim 3, wherein the step of filling the first source-drain doped layer comprises: removing the occupying layer; and filling a first source-drain doping layer at the original position of the occupying layer.
5. 5. The method of forming of claim 4, wherein the process of removing the placeholder layer comprises: Wet etching process.
6. 6. The method of claim 3, wherein removing the protective material layer at the top surface of the placeholder layer comprises: Ion etching process.
7. 7. The method of claim 6, wherein the etching selectivity of the ion etching process to the protective material layer at the top surface of the placeholder layer and the protective material layer at the side of the stacked structure is greater than or equal to 2:1.
8. 8. The method of forming of claim 3, wherein the step of filling the placeholder layer comprises: filling a space occupying material layer on the substrate between the stacked structure structures; And removing part of the thickness of the space occupying material layer, and using the space occupying material layer reserved on the side surface of the first channel structure as the space occupying layer.
9. 9. The method of forming of claim 2, wherein the stacked structure further comprises a second dielectric layer, the second dielectric layer being located between the first channel structure and the second channel structure, the step of forming the first dielectric layer comprising: Filling a dielectric material layer on the first source-drain doped layer; Removing part of the thickness of the dielectric material layer, and using the dielectric material layer reserved on the side surface of the second dielectric layer as a first intermediate dielectric layer; removing the protective layer covering the side surface of the second channel structure, wherein the protective layer reserved on the side surface of the second dielectric layer is used as a second intermediate dielectric layer; wherein the first intermediate dielectric layer and the second intermediate dielectric layer serve as the first dielectric layer.
10. 10. The method of claim 2, wherein the protective layer has a thickness of 1nm to 5nm.
11. 11. A semiconductor structure, comprising: A substrate; a plurality of stacked structures including a first channel structure on the substrate and a second channel structure on the first channel structure; the first source-drain doping layer is positioned on the substrate between the stacking structures and covers the side surface of the first channel structure; The first dielectric layer is positioned on the first source-drain doping layer; And the second source-drain doping layer is positioned on the first dielectric layer and covers the side surface of the second channel structure.
12. 12. The semiconductor structure of claim 11, the first dielectric layer comprising: The first intermediate dielectric layer is positioned on the first source-drain doping layer; and the second intermediate dielectric layer is positioned on the first source-drain doping layer and is positioned between the first intermediate dielectric layer and the stacking structure.
13. 13. The semiconductor structure of claim 12, wherein the material of the first intermediate dielectric layer is one or more of silicon nitride, silicon oxide, silicon oxycarbide, and silicon carbide nitride.
14. 14. The semiconductor structure of claim 12, wherein the material of the second intermediate dielectric layer is one or more of silicon nitride, silicon oxide, silicon oxycarbide, and silicon carbide nitride.
15. 15. The semiconductor structure of claim 11, wherein the stacked structure further comprises: And a second dielectric layer positioned between the first channel structure and the second channel structure.
16. 16. The semiconductor structure of claim 15, wherein the material of the second dielectric layer is one or more of silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, and silicon carbide nitride.

Description

Semiconductor structure and forming method thereof Technical Field The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same. Background With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, higher integration, and higher performance. When technology nodes come below 2nm, FINFET and GAA transistor fabrication has not been able to be reduced in size any further, and a new device structure CFET (Complementary field-effect transistor) is now able to further boost transistor density by stacking P-type and N-type transistors longitudinally, thus becoming one of the powerful candidates for continued advancement of moore's law. However, the manufacturing technology of the CFET device is still under continuous exploration, and the electrical performance of the CFET device is still to be improved. Disclosure of Invention In view of the above, embodiments of the present invention provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure. The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a plurality of stacked structures on the substrate, wherein the stacked structures comprise a first channel structure positioned on the substrate and a second channel structure positioned on the first channel structure, filling a first source drain doping layer on the substrate between the stacked structures, wherein the first source drain doping layer covers the side face of the first channel structure, forming a first dielectric layer on the first source drain doping layer, and filling a second source drain doping layer on the first dielectric layer, and the second source drain doping layer covers the side face of the second channel structure. The embodiment of the invention provides a semiconductor structure, which comprises a substrate, a plurality of stacked structures, a first source-drain doping layer, a first dielectric layer, a second source-drain doping layer and a second dielectric layer, wherein the stacked structures comprise a first channel structure positioned on the substrate and a second channel structure positioned on the first channel structure, the first source-drain doping layer is positioned on the substrate between the stacked structures and covers the side face of the first channel structure, the first dielectric layer is positioned on the first source-drain doping layer, and the second source-drain doping layer is positioned on the first dielectric layer and covers the side face of the second channel structure. Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages: In the technical scheme provided by the embodiment of the invention, the first dielectric layer is formed on the first source-drain doped layer, and the second source-drain doped layer is formed on the first dielectric layer, so that the electrical isolation between the first source-drain doped layer and the second source-drain doped layer can be realized through the first dielectric layer, the leakage current between the first source-drain doped layer and the second source-drain doped layer is reduced, the switching current ratio of the semiconductor structure is improved, and the performance of the semiconductor structure can be optimized. Drawings In order to more clearly illustrate the technical solutions of the embodiments of the present description, the drawings that are required to be used in the embodiments of the present description or the description of the prior art will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present description, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Fig. 1 to 11 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention. Detailed Description With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, higher integration, and higher performance. When technology nodes come below 2nm, FINFET and GAA transistor fabrication has not been able to be reduced in size any further, CFET (Complementary field-effect transistor) can further boost transistor density by stacking P-type and N-type transistors longitudinally, thus becoming one of the powerful candidates for continued advancement of moore's law. However, the source and drain of CFET are prone to current leakage, affecting the performance of CFET. In order to solve the technical problems, the embodiment of the invention p