CN-122028491-A - Integrated circuit and method of forming the same

Abstract

The integrated circuit includes a substrate having a first active region extending in a first direction, a second active region, and a third active region. The first active region and the second active region are closer together than the second active region and the third active region. The first isolation structure is located between and extends alongside the first active region and the second active region. The second isolation structure is located between and extends alongside the second and third active regions. The first isolation structure and the second isolation structure have different compositions. Embodiments of the application also relate to integrated circuits and methods of forming the same.

Inventors

• ZHOU JUNYI
• JIANG GUOCHENG
• WANG ZHIHAO
• FENG JIAXIN
• CHEN JIANHAO

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20251231

Priority Date

20250522

Claims (10)

1. 1. A method of forming an integrated circuit, comprising: forming a first active region extending longitudinally in a first direction over a substrate; forming a second active region extending longitudinally in the first direction over the substrate; Forming a third active region extending longitudinally in the first direction over the substrate; Forming a first isolation structure between and beside the first active region and the second active region; forming a second isolation structure between and beside the second active region and the third active region, wherein the second isolation structure has a different layer composition than the first isolation structure; Forming a channel region of a transistor in the first active region; Forming a source/drain region of the transistor coupled to the channel, wherein a portion of the source/drain region overhangs the first isolation structure in a second direction transverse to the first direction; Forming an etch stop layer over the source/drain regions, the first isolation structure, and the second isolation structure, and An interlayer dielectric layer is formed on the etch stop layer over the source/drain regions, the first isolation structure, and the second isolation structure.
2. 2. The method of claim 1, wherein the first isolation structure and the second isolation structure comprise a first dielectric layer and a second dielectric layer on the first dielectric layer, wherein a top surface of the second dielectric layer has a different shape in the first isolation structure than in the second isolation structure.
3. 3. The method of claim 2, wherein the second isolation structure comprises a third dielectric layer on the second dielectric layer.
4. 4. The method of claim 3, wherein the first and third dielectric layers comprise silicon oxide.
5. 5. The method of claim 4, wherein the second dielectric layer comprises silicon nitride.
6. 6. The method of claim 2, further comprising forming a metal layer over the first, second, and third active regions and over the first and second isolation structures.
7. 7. The method of claim 6, wherein the second dielectric layer has a U-shape in the second isolation structure under the gate metal, wherein the second dielectric layer has a flush and continuous top surface under the gate metal.
8. 8. The method of claim 6, wherein the third dielectric layer has a greater thickness under the gate metal than outside the gate metal.
9. 9. A method of forming an integrated circuit, comprising: Depositing a first dielectric layer of an isolation structure in a trench between a first active region and a second active region of an integrated circuit; Depositing a second dielectric layer of the isolation structure in the trench over the first dielectric layer; depositing a third dielectric layer of the isolation structure in the trench over the second dielectric layer; Forming a hard mask structure on the third dielectric layer; Forming a gate dielectric over the first active region, and A gate metal is formed over the gate dielectric layer and the hard mask structure over the isolation structure.
10. 10. An integrated circuit, comprising: A first active region, a second active region, and a third active region, the first active region extending in a first direction, the second active region extending in the first direction, and the third active region extending in the first direction; A first isolation structure located between and beside the first active region and the second active region; A second isolation structure located between and beside the second active region and the third active region, wherein the second isolation structure comprises more layers of dielectric material than the first isolation structure; a plurality of stacked channels located in the first active region; A source/drain region coupled to the stacked channel, wherein a portion of the source/drain region overhangs the first isolation structure in a second direction transverse to the first direction; A gate dielectric on the stacked channels, and And a gate metal over the gate dielectric layer, the first isolation structure, and the second isolation structure.

Description

Integrated circuit and method of forming the same Technical Field Embodiments of the application relate to integrated circuits and methods of forming the same. Background The semiconductor integrated circuit industry has experienced an exponential growth. Technological advances in integrated circuit materials and design have resulted in multi-generation integrated circuits, where each generation has smaller and more complex circuitry than the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such a shrink process generally provides benefits by improving production efficiency and reducing associated costs. Such scaling also increases the complexity of processing and manufacturing integrated circuits. Disclosure of Invention Some embodiments of the application provide a method of forming an integrated circuit comprising forming a first active region extending longitudinally in a first direction over a substrate, forming a second active region extending longitudinally in the first direction over the substrate, forming a third active region extending longitudinally in the first direction over the substrate, forming a first isolation structure between and beside the first active region and the second active region, forming a second isolation structure between and beside the second active region and the third active region, wherein the second isolation structure has a different combination of layers than the first isolation structure, forming a channel region of a transistor in the first active region, forming a source/drain region of the transistor coupled to the channel, wherein a portion of the source/drain region is suspended over the first isolation structure in a second direction transverse to the first direction, forming an etch stop layer over the source/drain region, the first isolation structure and the second isolation structure, and forming an etch stop layer over the first isolation layer and the first isolation layer. Further embodiments of the present application provide a method of forming an integrated circuit comprising depositing a first dielectric layer of an isolation structure in a trench between a first active region and a second active region of the integrated circuit, depositing a second dielectric layer of the isolation structure in the trench over the first dielectric layer, depositing a third dielectric layer of the isolation structure in the trench over the second dielectric layer, forming a hard mask structure over the third dielectric layer, forming a gate dielectric over the first active region, and forming a gate metal over the gate dielectric layer and the hard mask structure over the isolation structure. Still further embodiments of the present application provide an integrated circuit comprising a first active region, a second active region, and a third active region, the first active region extending in a first direction, the second active region extending in the first direction, and the third active region extending in the first direction, a first isolation structure between and beside the first active region and the second active region, a second isolation structure between and beside the second active region and the third active region, wherein the second isolation structure comprises more layers of dielectric material than the first isolation structure, a plurality of stacked channels in the first active region, source/drain regions coupled to the stacked channels, wherein portions of the source/drain regions overhang the first isolation structure in a second direction transverse to the first direction, a gate dielectric over the stacked channels, and a gate metal over the first isolation structure, and the second isolation structure. Drawings The various aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1-14 are cross-sectional and top views of an integrated circuit at various stages of processing according to some embodiments. Fig. 15 is a flow chart of a method of manufacturing an integrated circuit according to some embodiments. Fig. 16 is a flow chart of a method of manufacturing an integrated circuit according to some embodiments. Detailed Description The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the pre