CN-122028492-A - Method for forming semiconductor

CN122028492ACN 122028492 ACN122028492 ACN 122028492ACN-122028492-A

Abstract

A method of forming a semiconductor includes forming a metal gate structure stacked around a channel layer, forming a trench cutting the metal gate structure into two isolation segments, and forming a gate isolation structure in the trench. Forming the trench includes performing a plasma etching process on the metal gate structure, the plasma etching process including a first step and a second step subsequent to the first step. The first step has a first source power and a first bias power, and the second step has a second source power and a second bias power. The ratio of the first source power to the second source power is 1:1 to 5:1, and the first bias power is smaller than the second bias power.

Inventors

ZHANG RONGHAO
LI YIHONG
HUANG XIANZHONG
CHEN BINGHONG
LIN BINYAN

Assignees

台湾积体电路制造股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260116
Priority Date: 20250117

Claims (10)

1. A method of forming a semiconductor, comprising: providing a structure comprising: a substrate; a channel layer stack on the substrate; A metal gate structure disposed over and surrounding the channel layer stack and extending longitudinally in a first direction from a top view, an A plurality of source/drain components located at both sides of the metal gate structure and connected to the channel layer stack; Forming a trench extending vertically through the metal gate structure and extending longitudinally from the top view in a second direction perpendicular to the first direction, and A gate isolation feature and a conductive feature are formed in the trench, Wherein, from the top view, the conductive member is surrounded by the gate isolation member, Wherein forming the trench includes a plurality of plasma etch cycles, each of the plurality of plasma etch cycles including a first step and a second step, Wherein the first step has a first source power and a first bias power, the second step has a second source power and a second bias power, The first source power is different from the second source power, and the first bias power is smaller than the second bias power.
2. The method of claim 1, wherein the trench includes a first portion having a first width and a second portion having a second width smaller than the first width, Wherein the first portion and the second portion are connected, and Wherein the first width and the second width are along the first direction.
3. The method of claim 2, wherein the first portion of the trench has a first depth, a second depth, and a third depth from adjacent the second portion to intermediate the first portion, Wherein the first depth is greater than the third depth and the third depth is greater than the second depth.
4. The method of claim 1, wherein prior to forming the trench, further comprising: forming a patterned hard mask over the structure, the hard mask having an opening exposing the metal gate structure, and Wherein, prior to the first step, each of the plurality of plasma etch cycles further comprises: Forming an oxide layer along a sidewall of the opening, and A dry etching process is performed on the oxide layer to expose the metal gate structure.
5. The method of claim 1, wherein a sidewall of the trench has a wavy profile from the top view, Wherein a maximum difference between a peak and a valley of the wavy profile is 5nm to 80nm.
6. A method of forming a semiconductor, comprising: forming a metal gate structure surrounding a channel layer stack; Forming a trench cutting the metal gate structure into two isolated segments, and A gate isolation structure is formed in the trench, Wherein forming the trench includes performing a plasma etching process on the metal gate structure, the plasma etching process including a first step and a second step after the first step, Wherein the first step has a first source power and a first bias power, the second step has a second source power and a second bias power, Wherein the ratio of the first source power to the second source power is 1:1 to 5:1, and Wherein the first bias power is less than the second bias power.
7. The method of claim 6, wherein a depth of the trench varies from 10nm to 30nm.
8. The method of claim 6, wherein forming the trench prior to performing the plasma etch process further comprises: Forming a patterned hard mask over the metal gate structure, the patterned hard mask having an opening exposing the metal gate structure, Conformally depositing an oxide layer in the opening, and An etching process is performed on the oxide layer to expose the metal gate structure.
9. A method of forming a semiconductor, comprising: Receiving a structure includes: a substrate; A first channel layer stack over the substrate; a second channel layer stack over the first channel layer stack; an intermediate dielectric layer between the first and second channel layer stacks, and A gate structure, a gate electrode structure, above the first and second channel layer stacks and surrounding the first channel layer stack and the second channel layer stack; forming a trench to cut the gate structure into two isolated portions, and A gate isolation feature and an L-shaped conductive feature are formed in the trench, Wherein forming the trench includes performing a plurality of plasma etching processes having a source power and a dc bias power, Wherein at least one of the plurality of plasma etching processes includes a plasma generating step, an etching step, and a cleaning step, Wherein the source power has a first step increase from the plasma generating step to the etching step, Wherein the DC bias power has a second step increase from the plasma generating step to the etching step.
10. The method of claim 9, wherein the cleaning step includes purging an inert gas from the structure, and Wherein the source power and the dc bias power in the cleaning step are zero.

Description

Method for forming semiconductor Technical Field The present disclosure relates to a method of forming a semiconductor. Background The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Advances in integrated circuit materials and design techniques have resulted in a generation of yet another generation of integrated circuits, each of which is smaller and more complex than the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnected devices per unit wafer area) has increased as a whole, while the geometry (i.e., the smallest component (or line) that can be fabricated using a fabrication process) has decreased. Such a scaled down process may generally be beneficial by increasing production efficiency and reducing associated costs. This shrinking in size also increases the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are required to achieve these advances. For example, as the density of advanced IC technology nodes is further reduced with the introduction of stacked device structures, front side interconnect structures and back side interconnect structures may be required to facilitate electrical connection and/or operation of devices of the stacked device structures (e.g., upper and lower transistors thereof). For example, gate cutting features are formed to separate nearby metal gate structures. While existing interconnect structures and gate cutting members have generally been able to meet their intended use, they have not been satisfactory in various respects. Disclosure of Invention According to one embodiment of the disclosure, a method of forming a semiconductor includes providing a structure including a substrate, a channel layer stack on the substrate, a metal gate structure disposed over and surrounding the channel layer stack and extending longitudinally in a first direction from a top view, and a plurality of source/drain features on either side of the metal gate structure and connected to the channel layer stack, forming a trench extending vertically through the metal gate structure and extending longitudinally in a second direction perpendicular to the first direction from the top view, and forming a gate isolation feature and a conductive feature in the trench, wherein the conductive feature is surrounded by the gate isolation feature from the top view, wherein forming the trench includes a plurality of plasma etch cycles, each of the plasma etch cycles including a first step and a second step, wherein the first step has a first source power and a first bias power, the second step has a second source power and a second bias power, wherein the first source power is different from the second source power, and the first bias power is less than the second bias power. According to one embodiment of the disclosure, a method for forming a semiconductor includes forming a metal gate structure surrounding a channel layer stack, forming a trench cutting the metal gate structure into two isolation segments, and forming a gate isolation structure in the trench, wherein forming the trench includes performing a plasma etching process on the metal gate structure, the plasma etching process including a first step and a second step after the first step, wherein the first step has a first source power and a first bias power, the second step has a second source power and a second bias power, wherein a ratio of the first source power to the second source power is 1:1 to 5:1, and wherein the first bias power is less than the second bias power. According to one embodiment of the disclosure, a method of forming a semiconductor includes receiving a structure including a substrate, a first channel layer stack over the substrate, a second channel layer stack over the first channel layer stack, an intermediate dielectric layer between the first channel layer stack and the second channel layer stack, and a gate structure over and surrounding the first channel layer stack and the second channel layer stack, forming a trench to cut the gate structure into two isolated portions, and forming a gate isolation feature and an L-shaped conductive feature in the trench, wherein forming the trench includes performing a plurality of plasma etching processes having a source power and a DC bias power, wherein at least one of the plurality of plasma etching processes includes a plasma generating step, an etching step, and a cleaning step, wherein the source power has a first step increase from the plasma generating step to the etching step, wherein the DC bias power has a first step increase from the plasma generating step to the etching step. Drawings The various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It is noted that the various components are not drawn to scale according to