CN-122028493-A - Stacked transistor, preparation method thereof and electronic equipment

CN122028493ACN 122028493 ACN122028493 ACN 122028493ACN-122028493-A

Abstract

The application provides a stacked transistor, a preparation method thereof and electronic equipment. The preparation method of the stacked transistor comprises the steps of providing a first material layer, an insulating layer and a second material layer which are arranged from top to bottom, carrying out ion implantation on the first material layer to obtain a first deep well structure, forming a first shallow well structure based on one part of the first deep well structure, forming a first collector contact structure based on the other part of the first deep well structure and forming a first base contact structure and a first emitter based on the two different parts of the first shallow well structure, forming a first transistor by the first emitter, a first base formed by the residual first shallow well structure and a first collector formed by the residual first deep well structure, forming a first contact metal above the first collector contact structure, the first base contact structure and the first emitter respectively, and forming a second transistor based on the second material layer after overturning.

Inventors

WU HENG
LAN CHUAN
WANG RUNSHENG
LI MING
WU XUSHENG
ZHANG LIJIE
HUANG RU

Assignees

北京大学
北京知识产权运营管理有限公司

Dates

Publication Date: 20260512
Application Date: 20260128

Claims (10)

1. A method of fabricating a stacked transistor, comprising: Providing a laminated structure, wherein the laminated structure comprises a first material layer, an insulating layer and a second material layer which are arranged from top to bottom; performing ion implantation on the first material layer to obtain a first deep well structure; forming a first shallow well structure based on a portion of the first deep well structure, wherein the first shallow well structure and the first deep well structure are different in doping ion type; forming a first collector contact structure based on another part of the first deep well structure, and forming a first base contact structure and a first emitter based on two different parts of the first shallow well structure, respectively, wherein the first emitter, a first base formed by the remaining first shallow well structure and a first collector formed by the remaining first deep well structure form a first transistor; Forming a first contact metal over the first collector contact structure, the first base contact structure, and the first emitter, respectively; Flipping the first transistor; And forming a second transistor based on the second material layer.
2. The method of manufacturing of claim 1, wherein forming a first collector contact structure based on another portion of the first deep well structure comprises: implanting ions into another part of the first deep well structure to form the first collector contact structure, or Removing another part of the first deep well structure, and epitaxially doping to form the first collector contact structure at the position where the other part is removed; Wherein, based on two different parts in the first shallow well structure, respectively form first base contact structure and first emitter, include: respectively performing ion implantation on two different parts of the first shallow well structure to respectively form the first base contact structure and the first emitter, or Removing two different parts in the first shallow well structure, and respectively epitaxially doping to form the first base contact structure and the first emitter at the positions where the two parts are removed; The doping ion type of the first collector contact structure is the same as the doping ion type of the first emitter, and is different from the doping ion type of the first base contact structure.
3. The method according to claim 1 or 2, wherein the forming a second transistor based on the second material layer includes: performing ion implantation on the second material layer to obtain a second deep well structure; forming a second shallow well structure based on a portion of the second deep well structure, wherein the doping ion types of the second shallow well structure and the second deep well structure are different; forming a second collector contact structure based on another part of the second deep well structure, and forming a second base contact structure and a second emitter based on two different parts of the second shallow well structure, respectively, wherein the second emitter, a second base formed by the remaining second shallow well structure and a second collector formed by the remaining second deep well structure form a second transistor; a second contact metal is formed over the second collector contact structure, the second base contact structure, and the second emitter, respectively.
4. The method of claim 1 or 2, wherein the ion implanting the first material layer to obtain a first deep well structure comprises: Ion implantation is carried out on the first material layer so as to obtain a lightly doped material layer; Etching the lightly doped material layer to obtain a plurality of fin structures, wherein the first deep well structure is at least one fin structure in the fin structures; Forming a dummy gate structure on a first fin structure, wherein the first fin structure is a fin structure of the plurality of fin structures except for the first deep well structure; wherein after the forming a first shallow well structure based on a portion of the first deep well structure, the method further comprises: Etching the first fin structure which is not covered by the dummy gate structure by taking the dummy gate structure as a hard mask so as to form a source drain groove; Forming an initial source drain structure in the source drain trench by epitaxial mode based on the first fin structure covered by the dummy gate structure; Wherein, based on another part of the first deep well structure, a first collector contact structure is formed, and based on two different parts of the first shallow well structure, a first base contact structure and a first emitter are respectively formed, and further comprising: And doping the initial source-drain structure to form a source-drain structure.
5. The method of manufacturing according to claim 4, wherein the first collector contact structure, the first base contact structure, and the first emitter are disposed in this order along the extending direction of the fin structure.
6. The method of manufacturing according to claim 4, further comprising: removing the pseudo gate structure to form a metal gate structure, wherein the source-drain structure and the metal gate structure form a third transistor; Wherein, on the first collector contact structure, the first base contact structure and the first emitter, a first contact metal is formed respectively, and further comprising: and forming source-drain metal on the source-drain structure.
7. The method of claim 1 or 2, wherein the ion implanting the first material layer to obtain a first deep well structure comprises: performing ion implantation on the first material layer to obtain an initial first deep well structure; Sequentially etching the initial first deep well structure, the insulating layer and the second material layer by adopting the same etching process to form a fin-shaped structure, wherein a first part of the fin-shaped structure is formed after the initial first deep well structure is etched, the first part of the fin-shaped structure is the first deep well structure, and a second part of the fin-shaped structure is formed after the second material layer is etched; wherein the forming a second transistor based on the second material layer includes: the second transistor is formed based on a second portion of the fin structure.
8. A stacked transistor, characterized in that the stacked transistor is prepared by the preparation method according to any one of claims 1 to 7, wherein the stacked transistor comprises a first transistor, a second transistor and an insulating layer, the insulating layer is positioned between the first transistor and the second transistor, and the first transistor and the second transistor are arranged in a way of being opposite to each other; The first transistor comprises a base, a collector and an emitter, and a base contact structure connected with the base and a collector contact structure connected with the collector, wherein the base and the collector contact structure are above the collector, and the emitter and the base contact structure are above the base; The first transistor further includes a first contact metal connecting the emitter, the base contact structure, and the collector contact structure.
9. The stacked transistor according to claim 8, wherein the transistor type of the second transistor may be a field effect device and/or a bipolar device; wherein the field effect device comprises a fin field effect transistor, a ring gate field effect transistor, a fork field effect transistor and a planar field effect transistor.
10. An electronic device comprising a circuit board and a stacked transistor according to claim 8 or 9.

Description

Stacked transistor, preparation method thereof and electronic equipment Technical Field The application relates to the technical field of semiconductor preparation, in particular to a stacked transistor, a preparation method thereof and electronic equipment. Background While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors stacked transistor) further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits. The process of manufacturing the stacked transistor adopts a monolithic (monolithic) scheme or a sequential (sequential) scheme, which has problems of high difficulty and complexity in manufacturing the stacked transistor, and is difficult to be compatible with the stacking arrangement of the bipolar junction transistor (Bipolar Junction Transistor, BJT). Accordingly, there is still a need for continued improvement in the fabrication process of stacked transistors. Disclosure of Invention The embodiment of the application provides a stacked transistor, a preparation method thereof and electronic equipment, which can realize the stacked arrangement of single-sided bipolar junction transistors, save process steps and further enhance the flexibility of circuit design. The technical scheme of the embodiment of the application is realized as follows: The embodiment of the application provides a preparation method of a stacked transistor, which comprises providing a stacked structure, wherein the stacked structure comprises a first material layer, an insulating layer and a second material layer which are arranged from top to bottom, performing ion implantation on the first material layer to obtain a first deep well structure, forming a first shallow well structure based on one part of the first deep well structure, wherein doping ion types of the first shallow well structure and the first deep well structure are different, forming a first collector contact structure based on the other part of the first deep well structure, and respectively forming a first base contact structure and a first emitter based on the two different parts of the first shallow well structure, wherein the first emitter, a first base formed by the residual first shallow well structure and a first collector formed by the residual first deep well structure form a first transistor, respectively forming a first contact metal on the first collector contact structure, the first base contact structure and the first emitter, and forming a second transistor based on the second material layer. The embodiment of the application provides a preparation method of a stacked transistor, which is prepared by adopting the preparation method. The stacked transistor comprises a first transistor, a second transistor and an insulating layer, wherein the insulating layer is positioned between the first transistor and the second transistor, the first transistor and the second transistor are arranged in a back-to-back mode, the first transistor comprises a base electrode, a collector electrode and an emitter electrode, a base electrode contact structure connected with the base electrode and a collector electrode contact structure connected with the collector electrode, the base electrode and the collector electrode contact structure are arranged above the collector electrode, the emitter electrode and the base electrode contact structure are arranged above the base electrode, and the first transistor further comprises a first contact metal connected with the emitter electrode, the base electrode contact structure and the collector electrode contact structure. The embodiment of the application provides electronic equipment, which comprises a circuit board and the stacking transistor. The technical scheme provided by the embodiment of the application can comprise the following beneficial effects: In the embodiment of the application, a first deep well structure is formed by carrying out ion implantation on a first material layer, then a first shallow well structure and the first deep well structure are constructed by selective doping, three ends (an emitter, a base and a collector) of a first transistor and a contact structure thereof are finally formed, then a wafer is turned over, a second transistor is prepared by utilizing a second material layer, and finally three-dimensional stacking and signal extraction of the bipolar junction transistor are realized. In the process, the problem that the related stacked transistor technology is difficult to be compatible with the bipolar junction transistor is solved, the fact that the upper layer transistor and the lower layer transistor are led out from one side is achieved, and complexity of the preparation technology is effectively reduced. It is to be understood that both the