CN-122028494-A - Stacked transistor, preparation method thereof, device and electronic equipment

Abstract

The application provides a stacked transistor, a preparation method thereof, a device and electronic equipment, wherein the method comprises the steps of forming a stacked structure on a substrate; the stacked structure comprises a first sacrificial layer, a second active structure and a first active structure which are stacked from bottom to top in a first direction, a first transistor is formed based on the first active structure, a substrate is reversed and removed, the first sacrificial layer is removed, a first hard mask is formed in situ on the first sacrificial layer, the first hard mask is etched isotropically to form a second hard mask, the second orthographic projection of the second hard mask in the first direction falls into the first orthographic projection of the first hard mask in the first direction, the second active structure is etched under the etching blocking effect of the second hard mask to form a third active structure, the width of the third active structure in the second direction is smaller than the width of the second active structure in the second direction, the second direction is perpendicular to the first direction, the second hard mask is removed, and the second transistor is formed based on the third active structure.

Inventors

• WU HENG
• Cheng Yuji
• Peng Guanyue
• LI MING
• HUANG RU

Assignees

• 北京大学

Dates

Publication Date

20260512

Application Date

20260128

Claims (10)

1. 1. A method of fabricating a stacked transistor, comprising: the method comprises the steps of forming a stacked structure on a substrate, wherein the stacked structure comprises a first sacrificial layer, a second active structure and a first active structure which are stacked from bottom to top in a first direction, and the first active structure and the second active structure are formed by alternately stacking a first semiconductor material and a second semiconductor material; forming a first transistor based on the first active structure; Rewinding and removing the substrate; removing the first sacrificial layer and forming a first hard mask at the original position of the first sacrificial layer; isotropically etching the first hard mask to form a second hard mask, wherein the second orthographic projection of the second hard mask in the first direction falls into the first orthographic projection of the first hard mask in the first direction; Etching the second active structure under the etching blocking effect of the second hard mask to form a third active structure, wherein the width of the third active structure in the second direction is smaller than that of the second active structure in the second direction, and the second direction is perpendicular to the first direction; And removing the second hard mask, and forming a second transistor based on the third active structure, wherein the first transistor and the second transistor form the stacked transistor.
2. 2. The method of claim 1, wherein the step of determining the position of the substrate comprises, Before the first transistor is formed based on the first active structure, the method further comprises the steps of depositing an insulating material on the substrate to form a shallow trench isolation layer, wherein the shallow trench isolation layer wraps the first sacrificial layer and the second active structure; The method comprises the steps of rewinding and removing the substrate, wherein the method comprises the steps of rewinding a wafer, removing the substrate until the first surface of the shallow trench isolation layer is exposed, and the surface, which is in contact with the substrate, of the shallow trench isolation layer is the first surface.
3. 3. The method of claim 2, wherein the isotropically etching the first hard mask to form a second hard mask comprises: etching the shallow trench isolation layer with the preset height back until the side wall of the first hard mask is exposed; The side wall is etched in the second direction, and the second hard mask is formed.
4. 4. The method of claim 2, wherein the removing the first sacrificial layer and forming a first hard mask in situ of the first sacrificial layer comprises: Removing the first sacrificial layer to form a first groove; and depositing a mask material in the first groove to form the first hard mask.
5. 5. The method of claim 1, wherein forming a first transistor based on the first active structure comprises: Forming a first dummy gate structure of the first transistor based on the first active structure; forming a first source-drain epitaxy and a first source-drain metal of the first transistor in a source-drain region of the first transistor; Removing the first dummy gate structure and forming a first gate metal layer of the first transistor; and performing a subsequent interconnection process on the first gate metal and the first source drain metal to form a first subsequent interconnection layer of the first transistor.
6. 6. The method of claim 1, wherein forming a second transistor based on the third active structure comprises: forming a second dummy gate structure of the second transistor based on the third active structure; forming a second source-drain epitaxy and a second source-drain metal of the second transistor in a source-drain region of the second transistor; removing the second dummy gate structure and forming a second gate metal layer of the second transistor; And performing a subsequent interconnection process on the second gate metal and the second source drain metal to form a second subsequent interconnection layer of the second transistor.
7. 7. The method of claim 1, wherein the stacked structure further comprises a second sacrificial layer, wherein the second sacrificial layer is located between the first active structure and the second active structure; In the forming a first transistor based on the first active structure, the method further includes: removing the second sacrificial layer to form a second groove; and depositing an insulating material in the second groove to form an isolation layer, wherein the isolation layer is used for isolating the first active structure and the second active structure.
8. 8. A stacked transistor is characterized in that, the stacked transistor prepared by the method of any one of claims 1 to 7, comprising: The first transistor comprises a first active structure; A second transistor; the second transistor includes a third active structure; the first transistor and the second transistor are stacked in a first direction; The width of the third active structure in the second direction is smaller than that of the first active structure in the second direction, and the second direction is perpendicular to the first direction.
9. 9. A semiconductor device, comprising: A plurality of stacked transistors as claimed in claim 8; The stacked transistors are electrically connected through the back-end interconnection layer to form a functional circuit.
10. 10. An electronic device, comprising: A system motherboard; the semiconductor device of claim 9, wherein the semiconductor device is mounted on and electrically connected to the system motherboard.

Description

Stacked transistor, preparation method thereof, device and electronic equipment Technical Field The present application relates to semiconductor manufacturing technology, and in particular, to a stacked transistor, a method for manufacturing the stacked transistor, a device, and an electronic apparatus. Background As integrated circuits enter the Gate All Around (GAA) era, three-dimensional stacked transistors (e.g., CFET) significantly improve density and performance by extending moore's law through vertical integration of NMOS and PMOS. However, the transistors in this structure are difficult to achieve effective and accurate adjustment of the channel widths of the different transistors in the stacked transistors due to process limitations, and become a key bottleneck that restricts their performance from being fully released. Disclosure of Invention The embodiment of the application provides a stacked transistor, a preparation method thereof, a device and electronic equipment, which can solve the problem that the channel size of a back side transistor in the stacked transistor is difficult to adjust. The technical scheme of the embodiment of the application is realized as follows: The embodiment of the application provides a preparation method of a stacked transistor, which comprises the steps of forming a stacked structure on a substrate, wherein the stacked structure comprises a first sacrificial layer, a second active structure and a first active structure which are stacked from bottom to top in a first direction, the first active structure and the second active structure are formed by alternately stacking a first semiconductor material and a second semiconductor material, forming the first transistor based on the first active structure, reversing a wafer and removing the substrate, removing the first sacrificial layer, forming a first hard mask at the original position of the first sacrificial layer, isotropically etching the first hard mask to form a second hard mask, the second orthographic projection of the second hard mask in the first direction falls into the first orthographic projection of the first hard mask in the first direction, etching the second active structure under the etching blocking effect of the second hard mask to form a third active structure, the width of the third active structure in the second direction is smaller than the width of the second active structure in the second direction, removing the second hard mask is perpendicular to the first direction, and forming the second transistor based on the second transistor. In some possible embodiments, before forming the first transistor based on the first active structure, the method further comprises depositing an insulating material on the substrate to form a shallow trench isolation layer, wrapping the first sacrificial layer and the second active structure with the shallow trench isolation layer, rewinding and removing the substrate, including flipping the wafer, removing the substrate until a first surface of the shallow trench isolation layer is exposed, and the surface of the shallow trench isolation layer in contact with the substrate is the first surface. In some possible embodiments, isotropically etching the first hard mask to form a second hard mask includes etching back shallow trench isolation layers of a predetermined height until sidewalls of the first hard mask are exposed, and etching the sidewalls in a second direction to form the second hard mask. In some possible embodiments, removing the first sacrificial layer and forming a first hard mask in situ of the first sacrificial layer includes removing the first sacrificial layer to form a first recess, and depositing a mask material in the first recess to form the first hard mask. In some possible embodiments, forming the first transistor based on the first active structure comprises forming a first dummy gate structure of the first transistor based on the first active structure, forming a first source drain extension and a first source drain metal of the first transistor in a source drain region of the first transistor, removing the first dummy gate structure and forming a first gate metal layer of the first transistor, and performing a subsequent interconnect process on the first gate metal and the first source drain metal to form a first subsequent interconnect layer of the first transistor. In some possible embodiments, forming the second transistor based on the third active structure comprises forming a second dummy gate structure of the second transistor based on the third active structure, forming a second source drain extension and a second source drain metal of the second transistor in a source drain region of the second transistor, removing the second dummy gate structure and forming a second gate metal layer of the second transistor, and performing a subsequent interconnect process on the second gate metal and the second source drain metal to form a se