CN-122028496-A - Wafer-level MOS driving compound semiconductor combined device and manufacturing method thereof

Abstract

The application provides a wafer-level MOS driving compound semiconductor combined device and a manufacturing method thereof. The device comprises a composite substrate with a vertical lamination structure, and a semiconductor epitaxial layer, a lattice buffer layer and a compound semiconductor lamination are sequentially arranged from top to bottom. The enhancement MOSFET is integrated in a semiconductor epitaxial layer, and the depletion mode HEMT is composed of a compound semiconductor lamination. The source electrode of the MOSFET is connected with the compound semiconductor lamination through a conductive interconnection structure penetrating through the lattice buffer layer, the back surface of the device is provided with a drain electrode, and the drain electrode is connected with an internal channel of the HEMT through a back surface through hole. The application eliminates bonding wires in the traditional package, remarkably reduces parasitic inductance and reduces the size of the device through wafer-level vertical integration.

Inventors

• YAN SHUFAN

Assignees

• 上海华虹宏力半导体制造有限公司

Dates

Publication Date

20260512

Application Date

20260127

Claims (18)

1. 1. A wafer level MOS drive compound semiconductor combination device, comprising: The semiconductor device comprises a composite substrate, a semiconductor epitaxial layer, a lattice buffer layer and a compound semiconductor lamination layer, wherein the composite substrate is provided with a vertical lamination structure and is sequentially provided with the semiconductor epitaxial layer, the lattice buffer layer and the compound semiconductor lamination layer from a first surface to a second surface of the composite substrate; An enhancement mode metal oxide semiconductor field effect transistor integrated in the semiconductor epitaxial layer; A depletion type high electron mobility transistor composed of the compound semiconductor stack; The grid electrode of the enhanced metal oxide semiconductor field effect transistor is led out to the first surface of the combined device, and the source electrode of the enhanced metal oxide semiconductor field effect transistor is connected with one side, close to the first surface, of the compound semiconductor lamination layer through a conductive interconnection structure penetrating through the lattice buffer layer; And the second surface of the combined device is provided with a drain electrode, and the drain electrode is connected with an internal channel of the depletion type high electron mobility transistor through a second surface through hole penetrating through the bottom of the compound semiconductor lamination.
2. 2. The wafer level MOS driving compound semiconductor device as recited in claim 1, wherein the material of the semiconductor epitaxial layer is silicon.
3. 3. The wafer level MOS driving compound semiconductor device according to claim 1, wherein the compound semiconductor stack includes a barrier layer and a channel layer stacked in a direction from the first surface to the second surface.
4. 4. The wafer level MOS-driven compound semiconductor device as recited in claim 3, wherein the barrier layer and the channel layer are each a nitride semiconductor material.
5. 5. The wafer-level MOS driving compound semiconductor device as recited in claim 4, wherein the barrier layer is made of AlGaN, and the channel layer is made of GaN.
6. 6. The wafer level MOS-driven compound semiconductor device as recited in claim 3, wherein a dielectric layer is disposed between the conductive interconnect structure and the barrier layer.
7. 7. The wafer level MOS-driven compound semiconductor device as recited in claim 3, wherein the second-side via extends through the channel layer and terminates at an interface of the barrier layer and the channel layer.
8. 8. The wafer level MOS-driven compound semiconductor device as recited in claim 1, wherein the device is a normally-off device.
9. 9. A method for manufacturing a wafer-level MOS drive compound semiconductor combination device, comprising at least: providing a composite substrate, wherein the composite substrate points to the direction of a second surface from a first surface of the composite substrate and at least comprises a semiconductor epitaxial layer, a lattice buffer layer and a compound semiconductor lamination, and the material of the semiconductor epitaxial layer is different from that of the compound semiconductor lamination; Removing part of the semiconductor epitaxial layer, and forming an enhanced metal oxide semiconductor field effect transistor structure in the removed area, wherein the enhanced metal oxide semiconductor field effect transistor structure comprises a source electrode area and a grid electrode area; Forming a source interconnection structure, wherein the source interconnection structure extends from the source region to the lattice buffer layer, penetrates through the lattice buffer layer and stops from one side of the compound semiconductor lamination close to the first surface, so that the source region and the compound semiconductor lamination are connected; Forming a first surface metallization structure above the semiconductor epitaxial layer, wherein the first surface metallization structure comprises a gate electrode connected with the gate region and a source electrode connected with the source region; Step five, etching treatment is carried out on the second surface of the composite substrate to form a second surface through hole penetrating through the bottom layer material in the compound semiconductor lamination, and the second surface through hole exposes a heterojunction interface inside the compound semiconductor lamination; And step six, forming a second surface metallization electrode, wherein the second surface metallization electrode fills the second surface through hole and covers the second surface of the composite substrate to serve as a drain electrode of the combined device.
10. 10. The method of manufacturing a wafer level MOS driving compound semiconductor package according to claim 9, wherein in the first step, the material of the semiconductor epitaxial layer is silicon.
11. 11. The method of manufacturing a wafer-level MOS-driven compound semiconductor device according to claim 9, wherein in the first step, the compound semiconductor stack includes a barrier layer and a channel layer stacked in a direction from the first surface to the second surface.
12. 12. The method of manufacturing a wafer-level MOS-driven compound semiconductor device as set forth in claim 11, wherein in the first step, the barrier layer and the channel layer are each made of a nitride semiconductor material.
13. 13. The method of manufacturing a wafer-level MOS driving compound semiconductor device according to claim 12, wherein in the first step, the material of the barrier layer is AlGaN, and the material of the channel layer is GaN.
14. 14. The method of manufacturing a wafer-level MOS-driven compound semiconductor assembly as set forth in claim 9, wherein in the second step, the semiconductor epitaxial layer is used for manufacturing a driving tube, and the compound semiconductor stack is used for forming a depletion device.
15. 15. The method of manufacturing a wafer-level MOS drive compound semiconductor package according to claim 9, wherein in step three, the source interconnect structure is formed using a source bus etching process.
16. 16. The method of manufacturing a wafer level MOS driving compound semiconductor device according to claim 15, wherein in the third step, the source bus etching process controls an etching depth so as to pass through the lattice buffer layer and stay on a side of the compound semiconductor stack close to the first face to form an interconnection via.
17. 17. The method of manufacturing a wafer level MOS driving compound semiconductor device according to claim 16, further comprising a step of forming a dielectric layer on a surface of the compound semiconductor stack exposed at a bottom of the interconnect via after etching the interconnect via and before forming the conductive material in step three.
18. 18. The method of manufacturing a wafer level MOS driving compound semiconductor device according to claim 11, wherein in the step five, the second-side via hole forming process includes etching from one side of the channel layer in a normally-on device region, the etching depth penetrating the channel layer to reach an interface between the barrier layer and the channel layer.

Description

Wafer-level MOS driving compound semiconductor combined device and manufacturing method thereof Technical Field The invention relates to the technical field of semiconductors, in particular to a wafer-level MOS driving compound semiconductor combined device and a manufacturing method thereof. Background As a representative of the third generation of wide band gap semiconductor materials, compound semiconductors (e.g., gallium nitride GaN) have become core materials of next generation power semiconductor devices by virtue of their excellent physical properties such as high critical breakdown electric field, high electron saturation drift velocity, and high electron mobility. In the prior art route, mature compound semiconductor High Electron Mobility Transistors (HEMTs) are typically depletion mode (D-mode, i.e., normally on) devices. This is because the polarization effect naturally present at the heterojunction interface produces a high concentration of two-dimensional electron gas (2 DEG), resulting in the device being in a conducting state at zero gate voltage. However, in most power conversion applications, the power switching device is required to have a Normally-off (normal-off) characteristic for safety and circuit design considerations. To solve this problem, a common-source common-gate structure is commonly adopted in the industry to realize the normally-off characteristic. Conventional approaches typically include a low voltage enhancement silicon-based Metal Oxide Semiconductor Field Effect Transistor (MOSFET) packaged in series with a high voltage depletion mode compound semiconductor HEMT. Specifically, the drain of the MOSFET is connected to the source of the HEMT, the source of the MOSFET is the source of the integral device, the gate of the MOSFET is the gate of the integral device, and the gate of the HEMT is connected to the source of the MOSFET. However, this traditional package-level integration scheme based on discrete devices suffers from the following significant drawbacks: First, two individual chips (Die) need to be connected by metal bond wires. Bond wires introduce a non-negligible parasitic inductance. In the high-frequency and high-speed switching process of the device, the parasitic inductance can cause voltage overshoot and oscillation, increase switching loss, even possibly cause the device to be switched on by mistake, and seriously affect the stability and efficiency of the system. Secondly, two independent chips are integrated in the package, so that the package structure becomes complex, and the difficulty and cost of the package process are increased. Finally, since two chips and bonding wires need to be accommodated, the size of the packaged device is limited by physical space, and is difficult to further shrink, which is not in line with the urgent demands of the current power electronic equipment for high power density and miniaturization. Therefore, there is a need for a wafer level MOS drive compound semiconductor device and method of manufacturing the same that enables wafer level integration, eliminates inter-die bond wire parasitic inductance, and effectively reduces package size. Disclosure of Invention The application provides a wafer-level MOS driving compound semiconductor combined device and a forming method thereof, which are used for solving the problems of large parasitic inductance, complex packaging process and larger device size caused by adopting discrete device packaging in the prior art. The application provides a wafer-level MOS driving compound semiconductor combination device, which comprises: The semiconductor device comprises a composite substrate, a semiconductor epitaxial layer, a lattice buffer layer and a compound semiconductor lamination layer, wherein the composite substrate is provided with a vertical lamination structure and is sequentially provided with the semiconductor epitaxial layer, the lattice buffer layer and the compound semiconductor lamination layer from a first surface to a second surface of the composite substrate; An enhancement mode metal oxide semiconductor field effect transistor integrated in the semiconductor epitaxial layer; A depletion type high electron mobility transistor composed of the compound semiconductor stack; The grid electrode of the enhanced metal oxide semiconductor field effect transistor is led out to the first surface of the combined device, and the source electrode of the enhanced metal oxide semiconductor field effect transistor is connected with one side, close to the first surface, of the compound semiconductor lamination layer through a conductive interconnection structure penetrating through the lattice buffer layer; And the second surface of the combined device is provided with a drain electrode, and the drain electrode is connected with an internal channel of the depletion type high electron mobility transistor through a second surface through hole penetrating through the bottom of the compou