CN-122028497-A - Gallium integrated circuit chip and preparation method thereof

CN122028497ACN 122028497 ACN122028497 ACN 122028497ACN-122028497-A

Abstract

The invention discloses a gallium integrated circuit chip and a preparation method thereof, belonging to the technical field of semiconductor device integration. The gallium integrated circuit chip comprises a basic circuit module formed by connecting a main pipe device and an auxiliary pipe device, wherein the drain electrode of the auxiliary pipe device is connected with the grid electrode of the main pipe device, the source electrode of the main pipe device and the source electrode of the auxiliary pipe device are connected together, the grid electrodes of the main pipe device and the auxiliary pipe device receive inverted input signals, when the main pipe device generates grid voltage ringing due to the coupling of adjacent circuit switches, the conducted auxiliary pipe device provides a discharging path for grid charges of the main pipe device to inhibit erroneous conduction, the auxiliary pipe device is preferably integrated with the main pipe device in a single-chip mode, and a high-reliability device structure comprising a cylindrical P-GaN region, a double grid electrode and a field plate is adopted, and the chip can integrate an inverter formed by the GaN device to locally generate inverted control signals so as to simplify external driving. The invention also provides a corresponding preparation method. The invention effectively solves the ringing problem of the gallium nitride power integrated circuit without sacrificing the switching speed, and remarkably improves the reliability and integration of the system.

Inventors

MA SHENGHENG
WU YIZHEN
LI KEJU
WANG LIANSHAN

Assignees

中科(深圳)无线半导体有限公司

Dates

Publication Date: 20260512
Application Date: 20260410

Claims (10)

1. The gallium integrated circuit chip is characterized by comprising a basic circuit module formed by connecting a main pipe device and an auxiliary pipe device, wherein the main pipe device is an enhanced gallium nitride device, the auxiliary pipe device is a field effect type semiconductor switch device which is functionally adaptive to the main pipe device, the drain electrode of the auxiliary pipe device is connected with the grid electrode of the main pipe device and is externally connected with a first input signal, the grid electrode of the auxiliary pipe device is externally connected with a second input signal, the first input signal and the second input signal are in an inverse relation, the drain electrode of the main pipe device is configured as the drain electrode end of the basic circuit module, and the source electrode of the main pipe device is connected with the source electrode of the auxiliary pipe device and is configured as the source electrode end of the basic circuit module; The secondary pipe device is configured to be turned on in response to the second input signal to discharge gate charges of the primary pipe device to make a gate source voltage thereof lower than a threshold voltage when the primary pipe device has its gate potential raised due to voltage ringing generated by external circuit coupling, thereby suppressing erroneous conduction of the primary pipe device.
2. The gallium integrated circuit chip of claim 1, wherein the secondary pipe device is an enhanced gallium nitride device and is integrated with the primary pipe device on the same epitaxial structure of the wafer.
3. Gallium integrated circuit chip according to claim 2, wherein the primary and/or secondary pipe devices comprise: A substrate; a nitride semiconductor stack formed over the substrate, the nitride semiconductor stack including at least a channel layer and a barrier layer; Two separate columnar P-GAN regions formed in the gate region above the barrier layer; A gate dielectric stack covering the columnar P-GAN region and the region therebetween; and a first gate electrode formed on the gate dielectric stack and located between the two columnar P-GAN regions.
4. A gallium integrated circuit chip according to claim 3, wherein the host device further comprises: an etched recess formed in the barrier layer on a side of the gate region adjacent the drain; And the second gate electrode is formed in the etched groove and is electrically connected with the first gate electrode.
5. The gallium integrated circuit chip of claim 4, wherein the primary tube device further comprises a first field plate structure between its gate and source, and the secondary tube device further comprises a second field plate structure between its gate and drain.
6. The gallium integrated circuit chip of any of claims 3-5, wherein a spacing between the columnar P-GAN regions is greater than a width of a single columnar P-GAN region.
7. The gallium integrated circuit chip of claim 1, wherein the base circuit module further comprises a control unit connected to the gate of the secondary pipe device for providing the second input signal; the control unit comprises an inverter circuit, and the output end of the inverter circuit is connected to the grid electrode of the auxiliary pipe device; Wherein the inverter circuit is configured to receive a third input signal and output a logic signal inverted from the first input signal as the second input signal.
8. The gallium integrated circuit chip of claim 7, wherein the inverter circuit comprises a depletion gallium nitride transistor and an enhancement gallium nitride transistor connected in series.
9. A method of manufacturing a gallium integrated circuit chip according to any one of claims 2-5, comprising the steps of: s1, providing a substrate, and sequentially epitaxially growing a buffer layer, a channel layer, an insertion layer, a barrier layer and a P-GAN layer on the substrate; s2, patterning the P-GAN layer to form at least two groups of separated columnar P-GAN areas which respectively correspond to grid areas of the main pipe device and the auxiliary pipe device; s3, depositing a first dielectric layer on the barrier layer and the cylindrical P-GAN region; S4, depositing a second dielectric layer on the first dielectric layer; s5, selectively etching the first dielectric layer, the second dielectric layer and part of the barrier layer in a grid region corresponding to the main pipe device to form an etching groove; s6, depositing a third dielectric layer covering the second dielectric layer and the etched groove; s7, forming a source contact hole and a drain contact hole penetrating through the dielectric layer to the barrier layer, and forming a source electrode and a drain electrode; S8, forming a first gate electrode in a region corresponding to the space between the columnar P-GAN regions, forming a second gate electrode in the etched groove, and electrically connecting the first gate electrode with the second gate electrode; s9, forming a passivation layer covering the electrode and top interconnection metal so as to realize electrical connection between the main pipe device and the auxiliary pipe device and form the basic circuit module.
10. The method of manufacturing a gallium integrated circuit chip according to claim 9, wherein in step S8, a first field plate structure connected to the source of the main transistor device and a second field plate structure connected to the drain of the sub-transistor device are simultaneously formed.

Description

Gallium integrated circuit chip and preparation method thereof Technical Field The invention relates to the technical field of semiconductor devices, in particular to a gallium integrated circuit chip and a preparation method thereof. Background Gallium nitride (GaN) High Electron Mobility Transistor (HEMT) has great application potential in the field of power electronics by virtue of excellent material characteristics such as wide forbidden band, high critical breakdown electric field, high electron saturation drift speed and the like. Compared with the traditional silicon-based power device, the GaN HEMT can achieve higher switching frequency and power density, so that the size of passive elements is obviously reduced, and the efficiency and power density of a power supply system are improved. However, the extremely high switching speed of GaN devices also presents serious technical challenges, one of the most prominent problems being voltage and current ringing during switching. This phenomenon is mainly due to unavoidable parasitic inductances and parasitic capacitances in the power loop, which together form a high-frequency LC resonant circuit. When the device is switched at high speed in nanosecond time, the resonant circuit is excited by the drastic changes in voltage and current, thereby inducing strong high-frequency damped oscillations, i.e., ringing, on the switching waveform. The strong voltage ringing can bring a series of serious consequences, namely, firstly, the grid voltage of the device is coupled and raised and exceeds a threshold voltage, erroneous conduction is caused, the through short circuit of a bridge circuit is caused, and even the device is burnt out seriously, secondly, the repeated voltage overshoot and oscillation can increase the switching loss of the device and reduce the overall efficiency of the system, thirdly, the voltage stress aggravation can accelerate the degradation of the device, and the long-term reliability is affected. To suppress ringing, the prior art typically employs an external passive snubber circuit (such as an RC snubber network or RCD clamp circuit) or adds negative turn-off or resistive damping in the gate drive path. However, the methods have obvious disadvantages that the external buffer circuit can increase the number, volume and cost of additional elements, the loss of the external buffer circuit can offset the high-frequency high-efficiency advantage of the GaN device, the increase of the grid resistance can slow down the switching speed and inhibit ringing, but the switching loss can be obviously increased, the speed advantage of GaN is lost, and the complex multi-level grid driving can increase the complexity of the system and the control difficulty. Therefore, on the premise of keeping the high-speed switching advantage of the GaN device, the method effectively inhibits ringing and prevents erroneous conduction from the inside of the chip, and becomes a key problem to be solved in the technical development of the current GaN power integrated circuit. Disclosure of Invention Aiming at the voltage ringing caused by parasitic parameters and the error conduction caused by the parasitic parameters in the high-speed switching application of the existing gallium nitride power device, the invention provides a gallium integrated circuit chip and a preparation method thereof. In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: The gallium integrated circuit chip comprises a basic circuit module formed by connecting a main pipe device and an auxiliary pipe device, wherein the main pipe device is an enhanced gallium nitride device, the auxiliary pipe device is a field effect type semiconductor switch device which is functionally matched with the main pipe device, the drain electrode of the auxiliary pipe device is connected with the grid electrode of the main pipe device and is externally connected with a first input signal, the grid electrode of the auxiliary pipe device is externally connected with a second input signal, the first input signal and the second input signal are in an inverse relation, the drain electrode of the main pipe device is configured as a drain electrode end of the basic circuit module, and the source electrode of the main pipe device is connected with the source electrode of the auxiliary pipe device and is configured as a source electrode end of the basic circuit module; The secondary pipe device is configured to be turned on in response to the second input signal to discharge gate charges of the primary pipe device to make a gate source voltage thereof lower than a threshold voltage when the primary pipe device has its gate potential raised due to voltage ringing generated by external circuit coupling, thereby suppressing erroneous conduction of the primary pipe device. Specifically, the secondary pipe device is an enhanced gallium nitride device and is integrated with the primary p