CN-122028498-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Abstract

A semiconductor device includes a substrate having a front surface and a back surface. The device includes a first transistor disposed on a front surface of a substrate and including a first gate electrode and a first source/drain pattern disposed adjacent to the first gate electrode. The device includes a front surface dummy stack structure disposed on the first transistor and electrically floating, the front surface dummy stack structure extending from a lower end to an upper end, the lower end being spaced apart from the first transistor. The front surface dummy stack structure includes front surface dummy vias and front surface dummy conductive lines stacked alternately with the first gate electrode such that heat generated in the first transistor is transferred to an upper end of the front surface dummy stack structure through the plurality of front surface dummy vias and the plurality of front surface dummy conductive lines.

Inventors

• ZHENG MINGZHEN
• JIN ZHENGUI
• Zheng Yinguo
• ZHAO JINHUI
• XU XIUXING

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250624

Priority Date

20241101

Claims (20)

1. 1. A semiconductor device, comprising: a substrate including a front surface and a rear surface disposed opposite to the front surface in a vertical direction; A first transistor disposed on the front surface of the substrate and including a first gate electrode and a first source/drain pattern disposed adjacent to the first gate electrode along a direction vertical to the vertical direction, and A front surface dummy stack structure disposed on the first transistor and electrically floating, the front surface dummy stack structure extending in a vertical direction from a lower end to an upper end, the lower end being spaced apart from the first transistor in the vertical direction, Wherein the front surface dummy stack structure includes a plurality of front surface dummy vias and a plurality of front surface dummy conductive lines, the plurality of front surface dummy vias and the plurality of front surface dummy conductive lines being alternately stacked, and The plurality of front surface dummy vias and the plurality of front surface dummy conductive lines of the front surface dummy stack structure overlap the first gate electrode in a vertical direction.
2. 2. The semiconductor device according to claim 1, further comprising: a first wiring structure connected to the first gate electrode and one of the first source/drain patterns, and An upper insulating layer covering the first wiring structure and the front surface dummy stack structure, Wherein the first wiring structure includes a plurality of front surface vias and a plurality of front surface wires, an The upper end of the first wiring structure and the upper end of the front surface dummy stack structure are disposed at the same level along the vertical direction.
3. 3. The semiconductor device of claim 2, wherein an uppermost front surface wire of the plurality of front surface wires is not vertically overlapped with the plurality of front surface dummy vias and the plurality of front surface dummy wires.
4. 4. The semiconductor device according to claim 2, further comprising a support substrate on the upper insulating layer.
5. 5. The semiconductor device according to claim 1, wherein the first transistor is included in a first flip-flop circuit.
6. 6. The semiconductor device of claim 5, wherein the first gate electrode of the first transistor is configured to receive a test signal input.
7. 7. The semiconductor device according to claim 1, further comprising: a power line disposed on a rear surface of the substrate, Wherein the power line is connected to one of the first source/drain patterns of the first transistor.
8. 8. The semiconductor device according to claim 1, further comprising: a second transistor disposed on the front surface of the substrate and including a second gate electrode and a second source/drain pattern adjacent to the second gate electrode; A first power line disposed on the rear surface of the substrate and connected to one of the second source/drain patterns, and A rear surface dummy stack structure disposed on a rear surface of the substrate and electrically floating, the rear surface dummy stack structure extending in a vertical direction from a lower end to an upper end, the upper end being spaced apart from the second transistor in the vertical direction, Wherein the back surface dummy stack structure includes a plurality of back surface dummy vias and a plurality of back surface dummy conductive lines, the plurality of back surface dummy vias and the plurality of back surface dummy conductive lines being alternately stacked, and The plurality of rear surface dummy vias and the plurality of rear surface dummy conductive lines of the rear surface dummy stack structure overlap the second gate electrode in a vertical direction.
9. 9. The semiconductor device according to claim 8, further comprising: a second wiring structure provided on the rear surface of the substrate and connected to the first power supply line, Wherein the second wiring structure includes a plurality of back surface vias and a plurality of back surface wires, the plurality of back surface vias and the plurality of back surface wires being alternately stacked, and The lower end of the second wiring structure and the lower end of the rear surface dummy stack structure are disposed at the same level along the vertical direction.
10. 10. The semiconductor device according to claim 9, further comprising: a rear surface insulating layer disposed on the rear surface of the substrate and covering the lower end of the second wiring structure and the lower end of the rear surface dummy stack structure, and And an external connection terminal penetrating the rear surface insulating layer to be connected to a lower end of the second wiring structure.
11. 11. The semiconductor device according to claim 8, wherein the second transistor is included in a second flip-flop circuit.
12. 12. The semiconductor device of claim 11, wherein the second gate electrode of the second transistor is configured to receive a test signal input.
13. 13. The semiconductor device of claim 1, wherein an uppermost front surface dummy wire of the plurality of front surface dummy wires has a width greater than a width of a lowermost front surface dummy wire of the plurality of front surface dummy wires.
14. 14. A semiconductor device, comprising: a substrate including a front surface and a rear surface opposite to the front surface along a vertical direction of the semiconductor device; A first transistor disposed on a front surface of the substrate and including a first gate electrode and a first source/drain pattern adjacent to the first gate electrode; A first power line disposed on the rear surface of the substrate and connected to one of the first source/drain patterns, and A rear surface dummy stack structure disposed on a rear surface of the substrate and electrically floating, the rear surface dummy stack structure extending in a vertical direction from a lower end to an upper end, the upper end being spaced apart from the first transistor in the vertical direction, Wherein the back surface dummy stack structure includes a plurality of back surface dummy vias and a plurality of back surface dummy conductive lines, the plurality of back surface dummy vias and the plurality of back surface dummy conductive lines being alternately stacked, and The plurality of rear surface dummy vias and the plurality of rear surface dummy conductive lines of the rear surface dummy stack structure overlap the first gate electrode in a vertical direction.
15. 15. The semiconductor device according to claim 14, wherein the first transistor is included in a first flip-flop circuit.
16. 16. The semiconductor device of claim 15, wherein the first gate electrode of the first transistor is configured to receive a test signal input.
17. 17. The semiconductor device according to claim 14, further comprising a first wiring structure provided on a rear surface of the substrate and connected to the first power supply line, Wherein the first wiring structure includes a plurality of back surface vias and a plurality of back surface wires, the plurality of back surface vias and the plurality of back surface wires being alternately stacked, and The lower end of the first wiring structure and the lower end of the rear surface dummy stack structure are disposed at the same level along the vertical direction.
18. 18. The semiconductor device according to claim 17, further comprising: A rear surface insulating layer disposed on the rear surface of the substrate and covering the lower end of the first wiring structure and the lower end of the rear surface dummy stack structure, and And an external connection terminal penetrating the rear surface insulating layer to be connected to a lower end of the first wiring structure.
19. 19. A semiconductor device, comprising: a substrate including a front surface and a rear surface opposite to the front surface along a vertical direction of the semiconductor device; A first flip-flop circuit and a second flip-flop circuit disposed on the front surface of the substrate, wherein the first flip-flop circuit includes a first transistor disposed on the front surface of the substrate and including a first gate electrode and a first source/drain pattern adjacent to the first gate electrode, and wherein the second flip-flop circuit includes a second transistor disposed on the front surface of the substrate and including a second gate electrode and a second source/drain pattern adjacent to the second gate electrode; a front surface dummy stack structure disposed on the first transistor and electrically floating, the front surface dummy stack structure extending along a vertical direction from a lower end to an upper end, the lower end being spaced apart from the first transistor in the vertical direction; a first wiring structure disposed on the front surface of the substrate and connected to the first gate electrode and one of the first source/drain patterns; a first power line disposed on a rear surface of the substrate and connected to one of the second source/drain patterns; A rear surface dummy stack structure disposed on the rear surface of the substrate and electrically floating, and A second wiring structure provided on the rear surface of the substrate and connected to the first power supply line, Wherein the front surface dummy stack structure includes a plurality of front surface dummy vias and a plurality of front surface dummy conductive lines, the plurality of front surface dummy vias and the plurality of front surface dummy conductive lines being alternately stacked, The plurality of front surface dummy vias and the plurality of front surface dummy conductive lines of the front surface dummy stack structure vertically overlap the first gate electrode, The back surface dummy stack structure includes a plurality of back surface dummy vias and a plurality of back surface dummy conductive lines, the plurality of back surface dummy vias and the plurality of back surface dummy conductive lines being alternately stacked, and The plurality of rear surface dummy vias and the plurality of rear surface dummy conductive lines of the rear surface dummy stack structure overlap the second gate electrode in a vertical direction.
20. 20. The semiconductor device of claim 19, wherein the first wiring structure comprises a plurality of front surface vias and a plurality of front surface wires, the plurality of front surface vias and the plurality of front surface wires being alternately stacked, The upper end of the first wiring structure and the upper end of the front surface dummy stack structure are disposed at the same first level along the vertical direction, The uppermost front surface conductive line of the plurality of front surface conductive lines is not overlapped with the plurality of front surface dummy conductive lines in a vertical direction, The second wiring structure includes a plurality of back surface vias and a plurality of back surface wires, the plurality of back surface vias and the plurality of back surface wires being alternately stacked, The lower end of the second wiring structure and the lower end of the rear surface dummy stack structure are disposed at the same second level along the vertical direction, and The lowermost rear surface wire of the plurality of rear surface wires is not overlapped with the plurality of rear surface dummy wires in a vertical direction.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips The present application claims priority from korean patent application No. 10-2024-0153290 filed on 1 month 11 of 2024, the entire contents of which are incorporated herein by reference. Technical Field The present disclosure relates to a semiconductor device and a method for analyzing a failure thereof. Background The semiconductor device may include an integrated circuit composed of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). As semiconductor device dimensions and design rules gradually decrease, scaling of MOSFETs is accelerating. As the size of the MOSFET decreases, defects or malfunctions of the semiconductor device may occur. Fault analysis is widely used in the semiconductor industry and can detect defects in semiconductor devices such as integrated circuits. However, as the design of semiconductor devices becomes more complex, defect detection accuracy is deteriorating. Disclosure of Invention The present disclosure provides a semiconductor device whose failure can be easily analyzed. The present disclosure also provides methods for analyzing faults of semiconductor devices using improved consistency. According to an embodiment of the present disclosure, there is provided a semiconductor device including a substrate including a front surface and a rear surface opposite to each other, a first transistor disposed on the front surface of the substrate and including a first gate electrode and first source/drain patterns adjacent to both sides thereof, and a front surface dummy stack structure on the first transistor and electrically floating, wherein the front surface dummy stack structure includes front surface dummy vias and front surface dummy conductive lines alternately stacked and the front surface dummy vias and front surface dummy conductive lines constituting the front surface dummy stack structure vertically overlap the first gate electrode. In an embodiment according to the present disclosure, a semiconductor device includes a substrate including a front surface and a rear surface opposite to each other, a first transistor disposed on the front surface of the substrate and including a first gate electrode and first source/drain patterns adjacent to both sides thereof, a first power line disposed on the rear surface of the substrate and connected to one of the first source/drain patterns, and a rear surface dummy stack structure disposed on the rear surface of the substrate and electrically floating, wherein the rear surface dummy stack structure includes rear surface dummy vias and rear surface dummy conductive lines alternately stacked, and the rear surface dummy vias and the rear surface dummy conductive lines constituting the rear surface dummy stack structure vertically overlap with the first gate electrode. In an embodiment according to the present disclosure, a semiconductor device includes a substrate including a front surface and a rear surface opposite to each other, a first flip-flop circuit and a second flip-flop circuit disposed on the front surface of the substrate, the first transistor including a first gate electrode and first source/drain patterns adjacent to both sides thereof and being included in the first flip-flop circuit, the second transistor being disposed on the front surface of the substrate including a second gate electrode and second source/drain patterns adjacent to both sides thereof and being included in the second flip-flop circuit, a front surface dummy stack structure disposed on the first transistor and electrically floating the first gate electrode, a first power line disposed on the rear surface of the substrate and connected to one of the first source/drain patterns, a rear surface dummy stack structure disposed on the rear surface of the substrate and electrically floating the first flip-flop circuit, and a second wiring structure disposed on the front surface of the substrate and including a second gate electrode and second source/drain patterns adjacent to both sides thereof, wherein the front surface dummy line and the first surface dummy line are stacked on the front surface of the substrate and the first dummy line, the first surface dummy line and the second surface of the first dummy line are stacked on the front surface of the substrate and the first dummy line, the first dummy line and the first dummy line are stacked on the front surface of the first dummy line, the first surface and the first dummy line and the second surface of the first dummy line are stacked, the first dummy line and the second dummy line are stacked. In an embodiment according to the present disclosure, a method for analyzing a failure of a semiconductor device includes manufacturing a semiconductor device including a front surface dummy stack structure disposed on a substrate and a rear surface dummy stack structure disposed on a lower portion of the substrate, fin