CN-122028499-A - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Abstract

A semiconductor device includes a base structure extending in a first direction, a gate electrode disposed on the base structure, extending in a second direction, and spaced apart from each other in the first and second directions, a plurality of channel layers disposed on the base structure, spaced apart from each other in a third direction, and surrounded by the gate electrode, source/drain regions connected to the plurality of channel layers on opposite sides of the gate electrode, an isolation structure separating the gate electrode, the plurality of channel layers, and the source/drain regions in the second direction, and extending in the first direction, and a gate connection layer electrically connected to the first and second gate electrodes spaced apart from each other in the fourth direction, the gate connection layer disposed on the isolation structure and contacting an upper surface of the isolation structure.

Inventors

• Pu Panji
• PU ZHI
• JIN BINGCHENG
• Qian Kuanyong

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250714

Priority Date

20241112

Claims (20)

1. 1. A semiconductor device, the semiconductor device comprising: A base structure extending in a first direction; A plurality of gate electrodes including at least a first gate electrode and a second gate electrode disposed on the base structure and extending in a second direction perpendicular to the first direction, the plurality of gate electrodes being spaced apart from each other in the first direction and the second direction; A plurality of channel layers disposed on the base structure, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the first direction and the second direction, the plurality of channel layers being surrounded by the plurality of gate electrodes; Source/drain regions connected to the plurality of channel layers on opposite sides of the plurality of gate electrodes; An isolation structure separating the plurality of gate electrodes, the plurality of channel layers, and the source/drain regions in the second direction, the isolation structure extending in the first direction, and And a gate connection layer electrically connecting the first gate electrode and the second gate electrode, the first gate electrode and the second gate electrode being spaced apart from each other in a fourth direction intersecting the first direction and the second direction and perpendicular to the third direction, the gate connection layer being disposed on and contacting an upper surface of the isolation structure.
2. 2. The semiconductor device of claim 1, wherein: the gate connection layer includes a first side surface and a second side surface, and The first side surface is in contact with the first gate electrode and the second side surface is in contact with the second gate electrode.
3. 3. The semiconductor device of claim 1, wherein: The gate connection layer includes a first lower surface; Each of the plurality of gate electrodes includes an upper surface and a second lower surface, and The first lower surface is located at a height lower than the upper surface and higher than the second lower surface in the third direction.
4. 4. The semiconductor device of claim 1, further comprising: The gate electrode contacts the plug and, the gate contact plugs are disposed on and electrically connected to some of the plurality of gate electrodes, wherein, The gate connection layer includes a first upper surface; Each gate contact plug includes a second upper surface, and The first upper surface is located at a lower height than the second upper surface in the third direction.
5. 5. The semiconductor device of claim 1, wherein: The plurality of gate electrodes further includes third and fourth gate electrodes spaced apart from the first and second gate electrodes, respectively, in the second direction by the isolation structure, and The gate connection layer is spaced apart from the third gate electrode and the fourth gate electrode in the second direction.
6. 6. The semiconductor device of claim 5, further comprising: a gate contact plug, a first interconnection line, a via, and a second interconnection line sequentially disposed on the third gate electrode and the fourth gate electrode in the third direction, wherein, The third gate electrode and the fourth gate electrode are electrically connected to each other through the gate contact plug, the first interconnection line, the via, and the second interconnection line.
7. 7. The semiconductor device of claim 1, wherein: the gate connection layer includes a first upper surface; Each of the plurality of gate electrodes includes a second upper surface, and The first upper surface is coplanar with the second upper surface in the third direction.
8. 8. The semiconductor device of claim 7, wherein: the gate connection layer has a first thickness in the third direction; the plurality of gate electrodes having a second thickness in the third direction on an uppermost channel layer of the plurality of channel layers, and The first thickness is less than the second thickness.
9. 9. The semiconductor device according to claim 1, wherein the gate connection layer includes a region extending in the fourth direction, or includes a first region extending in the first direction and a second region extending in the second direction.
10. 10. The semiconductor device of claim 1, wherein: The gate connection layer includes a side surface, and A portion of the side surface is in contact with the isolation structure.
11. 11. The semiconductor device of claim 1, wherein the isolation structures have the same height between the plurality of gate electrodes and between the source/drain regions.
12. 12. The semiconductor device of claim 1, wherein the base structure comprises a semiconductor material or an insulating material.
13. 13. The semiconductor device of claim 1, further comprising: a back side contact plug penetrating the body structure and connected to a lower portion of at least one of the source/drain regions.
14. 14. A semiconductor device, the semiconductor device comprising: a first gate electrode and a second gate electrode spaced apart from each other in a first direction; third and fourth gate electrodes spaced apart from each other in the first direction and spaced apart from the first and second gate electrodes in a second direction perpendicular to the first direction; An isolation structure extending in the first direction between the first gate electrode and the third gate electrode and between the second gate electrode and the fourth gate electrode; A source/drain region located on opposite sides of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode in the first direction, the source/drain regions being spaced apart from each other in the second direction by the isolation structure, and And a gate connection layer disposed on the isolation structure, the gate connection layer having a side surface through which the second gate electrode and the third gate electrode are contacted and electrically connected.
15. 15. The semiconductor device of claim 14, wherein: the first gate electrode is electrically isolated from the third gate electrode by the isolation structure, and The second gate electrode is electrically isolated from the fourth gate electrode by the isolation structure.
16. 16. The semiconductor device of claim 14, further comprising: a gate contact plug disposed on the first gate electrode and the fourth gate electrode and on one of the second gate electrode or the third gate electrode.
17. 17. The semiconductor device of claim 14, wherein an upper surface of the gate connection layer is covered with an insulating material.
18. 18. The semiconductor device of claim 14, wherein the isolation structure comprises: a lower isolation structure between the first gate electrode and the third gate electrode and between the second gate electrode and the fourth gate electrode, and An upper isolation structure extending between the source/drain regions over the lower isolation structure.
19. 19. A semiconductor device, the semiconductor device comprising: gate structures spaced apart from each other in a first direction and a second direction perpendicular to the first direction, each gate structure including a gate dielectric layer, a gate electrode, and a gate capping layer sequentially stacked in a third direction perpendicular to the first direction and the second direction; A plurality of channel layers spaced apart from each other along the third direction and surrounded by the gate structure; source/drain regions connected to the plurality of channel layers on opposite sides of the gate structure; An isolation structure separating the gate structure, the plurality of channel layers, and the source/drain regions in the second direction, the isolation structure extending in the first direction, and And a gate connection layer disposed on the isolation structure and contacting the gate capping layer, the gate connection layer electrically connecting first and second gate electrodes spaced apart from each other in a fourth direction intersecting the first and second directions.
20. 20. The semiconductor device of claim 19, wherein: the gate connection layer includes a first upper surface; The gate cap layer includes a second upper surface, and The first upper surface is located at a height equal to or lower than the second upper surface in the third direction.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Technical Field The present disclosure relates to semiconductor devices. Background As the demand for high performance, high speed, and/or versatility of semiconductor devices increases, the integration level of semiconductor devices is increasing. In manufacturing a semiconductor device having a fine pattern corresponding to the trend of high integration of the semiconductor device, it is necessary to realize a pattern having a fine width or a fine separation distance. In addition, efforts are being made to develop a semiconductor device including a transistor having a three-dimensional channel structure to overcome limitations on the operation characteristics due to the reduction in size of a planar Metal Oxide Semiconductor FET (MOSFET). Disclosure of Invention An aspect of the present disclosure is to provide a semiconductor device having improved integration and electrical characteristics. In some embodiments, a semiconductor device includes a base structure extending in a first direction, a plurality of gate electrodes including at least a first gate electrode and a second gate electrode disposed on the base structure and extending in a second direction perpendicular to the first direction, the plurality of gate electrodes being spaced apart from each other in the first direction and the second direction, a plurality of channel layers disposed on the base structure and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, the plurality of channel layers being surrounded by the plurality of gate electrodes, a source/drain region connected to the plurality of gate electrodes on opposite sides of the plurality of gate electrodes, an isolation structure separating the plurality of gate electrodes, the plurality of channel layers, and the source/drain region in the second direction, the isolation structure extending in the first direction, and a gate connection layer disposed on the base structure and spaced apart from each other in a third direction perpendicular to the first direction, the gate connection layer and the gate electrode being electrically connected to the second gate electrode and the second gate electrode being spaced apart from the first gate electrode and the second gate electrode in the third direction. In some embodiments, a semiconductor device includes first and second gate electrodes spaced apart from each other in a first direction, third and fourth gate electrodes spaced apart from each other in the first direction and spaced apart from the first and second gate electrodes in a second direction perpendicular to the first direction, an isolation structure extending between the first and third gate electrodes and between the second and fourth gate electrodes in the first direction, source/drain regions located on opposite sides of the first, second, third and fourth gate electrodes in the first direction, the source/drain regions spaced apart from each other in the second direction by the isolation structure, and a gate connection layer disposed on the gate connection layer, the gate connection layer having a side surface electrically contacting the gate structures and the third electrode. In some embodiments, a semiconductor device includes gate structures spaced apart from each other in a first direction and a second direction perpendicular to the first direction, each gate structure including a gate dielectric layer, a gate electrode, and a gate capping layer sequentially stacked in a third direction perpendicular to the first direction and the second direction, a plurality of channel layers spaced apart from each other along the third direction, the plurality of channel layers surrounded by the gate structures, source/drain regions connected to the plurality of channel layers on opposite sides of the gate structures, an isolation structure separating the gate structures, the plurality of channel layers, and the source/drain regions in the second direction, the isolation structure extending in the first direction, and a gate connection layer disposed on the isolation structure, contacting the gate capping layer, and electrically connecting first and second gate electrodes, the first and second gate electrodes spaced apart from each other in the first and second directions. Drawings The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: Fig. 1 is a top view illustrating a semiconductor device according to some embodiments. Fig. 2A-2C are cross-sectional views illustrating semiconductor devices according to some embodiments. Fig. 3A and 3B are layout diagrams illustrating semiconductor devices according to some embodiments. Fig. 4A and 4B are cross-sectional views illustrating se